mpc83xx: MPC8360E-RDK: use RGMII_RXID interface mode

[u-boot] / include / configs / MPC8360ERDK.h

diff --git a/include/configs/MPC8360ERDK.h b/include/configs/MPC8360ERDK.h
index e6d0c5e98ee492179fd3f62621538600dfe0f06c..1588610b87c07316fdd74e7dc8add37f158b5c44 100644 (file)
--- a/include/configs/MPC8360ERDK.h
+++ b/include/configs/MPC8360ERDK.h
@@ -17,8 +17,6 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#undef DEBUG
-
 /*
  * High Level Configuration Options
  */
@@ -241,7 +239,7 @@
 #define CONFIG_I2C_CMD_TREE
 #define CFG_I2C_SPEED  400000  /* I2C speed and slave address */
 #define CFG_I2C_SLAVE  0x7F
-#define CFG_I2C_NOPROBES       {0x52} /* Don't probe these addrs */
+#define CFG_I2C_NOPROBES       {{0x52}} /* Don't probe these addrs */
 #define CFG_I2C_OFFSET 0x3000
 #define CFG_I2C2_OFFSET 0x3100
 
@@ -282,7 +280,7 @@
  * QE UEC ethernet configuration
  */
 #define CONFIG_UEC_ETH
-#define CONFIG_ETHPRIME                "Freescale GETH"
+#define CONFIG_ETHPRIME                "FSL UEC0"
 
 #define CONFIG_UEC_ETH1                /* GETH1 */
 
@@ -292,7 +290,7 @@
 #define CFG_UEC1_TX_CLK                QE_CLK9
 #define CFG_UEC1_ETH_TYPE      GIGA_ETH
 #define CFG_UEC1_PHY_ADDR      2
-#define CFG_UEC1_INTERFACE_MODE ENET_1000_GMII
+#define CFG_UEC1_INTERFACE_MODE ENET_1000_RGMII_RXID
 #endif
 
 #define CONFIG_UEC_ETH2                /* GETH2 */
@@ -303,7 +301,7 @@
 #define CFG_UEC2_TX_CLK                QE_CLK4
 #define CFG_UEC2_ETH_TYPE      GIGA_ETH
 #define CFG_UEC2_PHY_ADDR      4
-#define CFG_UEC2_INTERFACE_MODE ENET_1000_GMII
+#define CFG_UEC2_INTERFACE_MODE ENET_1000_RGMII_RXID
 #endif
 
 /*
@@ -386,15 +384,6 @@
 #define CFG_HID0_FINAL         HID0_ENABLE_MACHINE_CHECK
 #define CFG_HID2               HID2_HBE
 
-/*
- * Cache Config
- */
-#define CFG_DCACHE_SIZE                32768
-#define CFG_CACHELINE_SIZE     32
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT    5 /*log base 2 of the above value */
-#endif
-
 /*
  * MMU Setup
  */