85xx: Convert MPC8544 DS to new TLB setup

[u-boot] / include / configs / MPC8540EVAL.h

diff --git a/include/configs/MPC8540EVAL.h b/include/configs/MPC8540EVAL.h
index dea061abee9d007a764a1071326840257534e845..bf64f27049c9bd785d1a7ef161608dc2a6abbe96 100644 (file)
--- a/include/configs/MPC8540EVAL.h
+++ b/include/configs/MPC8540EVAL.h
@@ -43,6 +43,8 @@
 #undef  CONFIG_DDR_ECC                     /* only for ECC DDR module */
 #define CONFIG_DDR_DLL                      /* possible DLL fix needed */
 
+#define CONFIG_FSL_LAW         1       /* Use common FSL init code */
+
 /* Using Localbus SDRAM to emulate flash before we can program the flash,
  * normally you only need a flash-boot image(u-boot.bin),if unsure undef this.
  * Not availabe for EVAL board
@@ -213,10 +215,13 @@
 #define CONFIG_NET_MULTI       1
 #define CONFIG_MII             1       /* MII PHY management   */
 #define CONFIG_TSEC1    1
+#define CONFIG_HAS_ETH0
 #define CONFIG_TSEC1_NAME      "TSEC0"
 #define CONFIG_TSEC2   1
+#define CONFIG_HAS_ETH1
 #define CONFIG_TSEC2_NAME      "TSEC1"
 #define CONFIG_MPC85XX_FEC      1
+#define CONFIG_HAS_ETH2
 #define CONFIG_MPC85XX_FEC_NAME                "FEC"
 #define TSEC1_PHY_ADDR          7
 #define        TSEC2_PHY_ADDR          4
@@ -224,6 +229,10 @@
 #define TSEC1_PHYIDX            0
 #define TSEC2_PHYIDX            0
 #define FEC_PHYIDX              0
+#define TSEC1_FLAGS            TSEC_GIGABIT
+#define TSEC2_FLAGS            TSEC_GIGABIT
+#define FEC_FLAGS              0
+
 /* Options are: TSEC[0-1], FEC */
 #define CONFIG_ETHPRIME                "TSEC0"
 
@@ -260,6 +269,15 @@
 #define CFG_LOADS_BAUD_CHANGE  1       /* allow baudrate change        */
 
 
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
 /*
  * Command line configuration.
  */
@@ -303,13 +321,6 @@
  */
 #define CFG_BOOTMAPSZ  (8 << 20)       /* Initial Memory map for Linux */
 
-/* Cache Configuration */
-#define CFG_DCACHE_SIZE        32768
-#define CFG_CACHELINE_SIZE     32
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT    5       /* log base 2 of the above value */
-#endif
-
 /*
  * Internal Definitions
  *