DaVinci DM6467: Enhance board Support

[u-boot] / include / configs / MPC8569MDS.h

diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h
index c7973b46a258a5236c443a2f5813a3083f17a743..9e24e1290721e74fb6faa64fd82c487f176d3eec 100644 (file)
--- a/include/configs/MPC8569MDS.h
+++ b/include/configs/MPC8569MDS.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2009-2010 Freescale Semiconductor, Inc.
+ * Copyright 2009-2011 Freescale Semiconductor, Inc.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -35,6 +35,9 @@
 
 #define CONFIG_FSL_ELBC                1       /* Has Enhance localbus controller */
 
+#define CONFIG_SYS_SRIO
+#define CONFIG_SRIO1                   /* SRIO port 1 */
+
 #define CONFIG_PCI             1       /* Disable PCI/PCIE */
 #define CONFIG_PCIE1           1       /* PCIE controller */
 #define CONFIG_FSL_PCI_INIT    1       /* use common fsl pci init code */
@@ -122,7 +125,6 @@ extern unsigned long get_clock_freq(void);
 #undef CONFIG_FSL_DDR_INTERACTIVE
 #define CONFIG_SPD_EEPROM              /* Use SPD EEPROM for DDR setup*/
 #define CONFIG_DDR_SPD
-#define CONFIG_DDR_DLL                 /* possible DLL fix needed */
 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER      /* DDR controller or DMA? */
 
 #define CONFIG_MEM_INIT_VALUE  0xDeadBeef
@@ -203,8 +205,9 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_FLASH_ERASE_TOUT    60000   /* Flash Erase Timeout (ms) */
 #define CONFIG_SYS_FLASH_WRITE_TOUT    500     /* Flash Write Timeout (ms) */
 
-#if defined(CONFIG_SYS_SPL) || defined(CONFIG_RAMBOOT_NAND)
+#if defined(CONFIG_RAMBOOT_NAND)
 #define CONFIG_SYS_RAMBOOT
+#define CONFIG_SYS_EXTRA_ENV_RELOC
 #else
 #undef CONFIG_SYS_RAMBOOT
 #endif
@@ -262,12 +265,6 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_OR3_PRELIM  CONFIG_NAND_OR_PRELIM /* NAND Options */
 #endif
 
-/*
- * SDRAM on the LocalBus
- */
-#define CONFIG_SYS_LBC_SDRAM_BASE      0xf0000000      /* Localbus SDRAM        */
-#define CONFIG_SYS_LBC_SDRAM_SIZE      64              /* LBC SDRAM is 64MB */
-
 #define CONFIG_SYS_LBC_LCRR    0x00000004      /* LB clock ratio reg */
 #define CONFIG_SYS_LBC_LBCR    0x00040000      /* LB config reg */
 #define CONFIG_SYS_LBC_LSRT    0x20000000      /* LB sdram refresh timer */
@@ -351,6 +348,7 @@ extern unsigned long get_clock_freq(void);
  * General PCI
  * Memory Addresses are mapped 1-1. I/O is mapped from 0
  */
+#define CONFIG_SYS_PCIE1_NAME          "Slot"
 #define CONFIG_SYS_PCIE1_MEM_VIRT      0xa0000000
 #define CONFIG_SYS_PCIE1_MEM_BUS       0xa0000000
 #define CONFIG_SYS_PCIE1_MEM_PHYS      0xa0000000
@@ -360,9 +358,10 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_PCIE1_IO_PHYS       0xe2800000
 #define CONFIG_SYS_PCIE1_IO_SIZE       0x00800000      /* 8M */
 
-#define CONFIG_SYS_SRIO_MEM_VIRT       0xc0000000
-#define CONFIG_SYS_SRIO_MEM_BUS                0xc0000000
-#define CONFIG_SYS_SRIO_MEM_PHYS       0xc0000000
+#define CONFIG_SYS_SRIO1_MEM_VIRT      0xC0000000
+#define CONFIG_SYS_SRIO1_MEM_BUS       0xC0000000
+#define CONFIG_SYS_SRIO1_MEM_PHYS      CONFIG_SYS_SRIO1_MEM_BUS
+#define CONFIG_SYS_SRIO1_MEM_SIZE      0x20000000      /* 512M */
 
 #ifdef CONFIG_QE
 /*
@@ -560,6 +559,7 @@ extern unsigned long get_clock_freq(void);
 
 #ifdef CONFIG_MMC
 #define CONFIG_FSL_ESDHC
+#define CONFIG_FSL_ESDHC_PIN_MUX
 #define CONFIG_SYS_FSL_ESDHC_ADDR      CONFIG_SYS_MPC85xx_ESDHC_ADDR
 #define CONFIG_CMD_MMC
 #define CONFIG_GENERIC_MMC
@@ -593,8 +593,8 @@ extern unsigned long get_clock_freq(void);
  * have to be in the first 16 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CONFIG_SYS_BOOTMAPSZ   (16 << 20)
-                                       /* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTMAPSZ   (16 << 20) /* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTM_LEN   (16 << 20)      /* Increase max gunzip size */
 
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE   230400  /* speed to run kgdb serial port */