#define CFG_RESET_ADDRESS 0xfff00100
-#undef CONFIG_PCI
+/*#undef CONFIG_PCI*/
+#define CONFIG_PCI
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
#define CFG_MEMTEST_START 0x00200000 /* memtest region */
#define CFG_MEMTEST_END 0x00400000
-
/*
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
#define CFG_CCSRBAR 0xf8000000 /* relocated CCSRBAR */
#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
-
/*
* DDR Setup
*/
#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
+#define CONFIG_VERY_BIG_RAM
#define MPC86xx_DDR_SDRAM_CLK_CNTL
#define CFG_DDR_CS5_BNDS 0x00000FFF /* Not done */
#endif
+#define CFG_ID_EEPROM 1
+#define ID_EEPROM_ADDR 0x57
/*
* In MPC8641HPCN, allocate 16MB flash spaces at fe000000 and ff000000.
#undef CFG_RAMBOOT
#endif
-#if !defined(CONFIG_SPD_EEPROM) && !defined(CFG_RAMBOOT)
-#undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
+#if defined(CFG_RAMBOOT)
+#undef CFG_FLASH_CFI_DRIVER
+#undef CONFIG_SPD_EEPROM
+#define CFG_SDRAM_SIZE 256
#endif
#undef CONFIG_CLOCKS_IN_MHZ
#define OF_CPU "PowerPC,8641@0"
#define OF_SOC "soc8641@f8000000"
-#define OF_TBCLK (bd->bi_busfreq / 8)
+#define OF_TBCLK (bd->bi_busfreq / 4)
#define OF_STDOUT_PATH "/soc8641@f8000000/serial@4500"
#define CFG_64BIT_VSPRINTF 1
/*
* I2C
*/
-#define CONFIG_HARD_I2C /* I2C with hardware support*/
+#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C /* I2C with hardware support*/
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
+#define CFG_I2C_OFFSET 0x3100
/*
* RapidIO MMU
#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE
#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */
+/* PCI view of System Memory */
+#define CFG_PCI_MEMORY_BUS 0x00000000
+#define CFG_PCI_MEMORY_PHYS 0x00000000
+#define CFG_PCI_MEMORY_SIZE 0x80000000
+
/* For RTL8139 */
+#define KSEG1ADDR(x) ({u32 _x=le32_to_cpu(*(u32 *)(x)); (&_x);})
#define _IO_BASE 0x00000000
#define CFG_PCI2_MEM_BASE 0xa0000000
#define CFG_PCI2_IO_PHYS CFG_PCI2_IO_BASE
#define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */
-
#if defined(CONFIG_PCI)
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#endif /* CONFIG_PCI */
+#define CONFIG_DOS_PARTITION
+#define CONFIG_SCSI_AHCI
+#ifdef CONFIG_SCSI_AHCI
+#define CONFIG_SATA_ULI5288
+#define CFG_SCSI_MAX_SCSI_ID 4
+#define CFG_SCSI_MAX_LUN 1
+#define CFG_SCSI_MAX_DEVICE (CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN)
+#define CFG_SCSI_MAXDEVICE CFG_SCSI_MAX_DEVICE
+#endif
+
+#endif /* CONFIG_PCI */
#if defined(CONFIG_TSEC_ENET)
#endif /* CONFIG_TSEC_ENET */
-
/*
* BAT0 2G Cacheable, non-guarded
* 0x0000_0000 2G DDR
*/
-#define CFG_DBAT0L ( BATL_PP_RW | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE | BATL_MEMCOHERENCE )
-#define CFG_DBAT0U ( BATU_BL_2G | BATU_VS | BATU_VP )
-#define CFG_IBAT0L ( BATL_PP_RW | BATL_CACHEINHIBIT | BATL_MEMCOHERENCE)
+#define CFG_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
+#define CFG_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP)
+#define CFG_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE )
#define CFG_IBAT0U CFG_DBAT0U
/*
* BAT6 32M Cache-inhibited, guarded
* 0xfe00_0000 32M FLASH
*/
-#define CFG_DBAT6L ( CFG_FLASH_BASE | BATL_PP_RW \
+#define CFG_DBAT6L ((CFG_FLASH_BASE & 0xfe000000) | BATL_PP_RW \
| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_DBAT6U (CFG_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
-#define CFG_IBAT6L (CFG_FLASH_BASE | BATL_PP_RW | BATL_MEMCOHERENCE)
+#define CFG_DBAT6U ((CFG_FLASH_BASE & 0xfe000000) | BATU_BL_32M | BATU_VS | BATU_VP)
+#define CFG_IBAT6L ((CFG_FLASH_BASE & 0xfe000000) | BATL_PP_RW | BATL_MEMCOHERENCE)
#define CFG_IBAT6U CFG_DBAT6U
#define CFG_DBAT7L 0x00000000
#define CFG_IBAT7L 0x00000000
#define CFG_IBAT7U 0x00000000
-
-
-
/*
* Environment
*/
#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
| CFG_CMD_PING \
| CFG_CMD_PCI \
- | CFG_CMD_I2C) \
+ | CFG_CMD_I2C \
+ | CFG_CMD_SCSI \
+ | CFG_CMD_EXT2) \
& \
~(CFG_CMD_ENV \
| CFG_CMD_IMLS \
#else
#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
| CFG_CMD_PING \
- | CFG_CMD_I2C) \
+ | CFG_CMD_I2C \
+ | CFG_CMD_SCSI \
+ | CGF_CMD_EXT2) \
& \
~(CFG_CMD_ENV \
| CFG_CMD_IMLS \
#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
| CFG_CMD_PCI \
| CFG_CMD_PING \
- | CFG_CMD_I2C)
+ | CFG_CMD_I2C \
+ | CFG_CMD_SCSI \
+ | CFG_CMD_EXT2)
#else
#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
| CFG_CMD_PING \
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
-
/*
* Environment Configuration
*/
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"consoledev=ttyS0\0" \
- "ramdiskaddr=400000\0" \
+ "ramdiskaddr=2000000\0" \
"ramdiskfile=your.ramdisk.u-boot\0" \
- "pex0=echo ---------------------------; echo --------- PCI EXPRESS -----\0"\
- "pexstat=mw f8008000 84000004; echo -expect:- 16000000; md f8008004 1\0" \
- "pex1=pci write 1.0.0 4 146; pci write 1.0.0 10 80000000\0" \
- "pexd=echo -expect:- xxx01002 00100146; pci display 1.0.0 0 2\0" \
- "pex=run pexstat; run pex1; run pexd\0" \
+ "dtbaddr=400000\0" \
+ "dtbfile=mpc8641_hpcn.dtb\0" \
"en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \
"dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \
"maxcpus=2"
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
"console=$consoledev,$baudrate $othbootargs;" \
"tftp $loadaddr $bootfile;" \
- "bootm $loadaddr"
+ "tftp $dtbaddr $dtbfile;" \
+ "bootm $loadaddr - $dtbaddr"
#define CONFIG_RAMBOOTCOMMAND \
"setenv bootargs root=/dev/ram rw " \
"console=$consoledev,$baudrate $othbootargs;" \
"tftp $ramdiskaddr $ramdiskfile;" \
"tftp $loadaddr $bootfile;" \
- "bootm $loadaddr $ramdiskaddr"
+ "tftp $dtbaddr $dtbfile;" \
+ "bootm $loadaddr $ramdiskaddr $dtbaddr"
#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
projects / u-boot / blobdiff