Merge branch 'at91' of git://git.denx.de/u-boot-atmel

[u-boot] / include / configs / P2020DS.h

diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h
index 66be725c8a045a55441d7215d7f23504fec7ea2c..79ce2c0a8b087be82064da17d0dc056c5565248f 100644 (file)
--- a/include/configs/P2020DS.h
+++ b/include/configs/P2020DS.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2007-2009 Freescale Semiconductor, Inc.
+ * Copyright 2007-2010 Freescale Semiconductor, Inc.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -27,6 +27,8 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+#include "../board/freescale/common/ics307_clk.h"
+
 #ifdef CONFIG_MK_36BIT
 #define CONFIG_PHYS_64BIT
 #endif
@@ -54,17 +56,9 @@
 #define CONFIG_TSEC_ENET               /* tsec ethernet support */
 #define CONFIG_ENV_OVERWRITE
 
-#ifndef __ASSEMBLY__
-extern unsigned long calculate_board_sys_clk(unsigned long dummy);
-extern unsigned long calculate_board_ddr_clk(unsigned long dummy);
-/* extern unsigned long get_board_sys_clk(unsigned long dummy); */
-/* extern unsigned long get_board_ddr_clk(unsigned long dummy); */
-#endif
-#define CONFIG_SYS_CLK_FREQ    calculate_board_sys_clk(0) /* sysclk for MPC85xx */
-#define CONFIG_DDR_CLK_FREQ    calculate_board_ddr_clk(0) /* ddrclk for MPC85xx */
+#define CONFIG_SYS_CLK_FREQ    get_board_sys_clk() /* sysclk for MPC85xx */
+#define CONFIG_DDR_CLK_FREQ    get_board_ddr_clk() /* ddrclk for MPC85xx */
 #define CONFIG_ICS307_REFCLK_HZ        33333000  /* ICS307 clock chip ref freq */
-#define CONFIG_GET_CLK_FROM_ICS307       /* decode sysclk and ddrclk freq
-                                            from ICS307 instead of switches */
 
 /*
  * These can be toggled for performance analysis, otherwise use default.
@@ -96,13 +90,13 @@ extern unsigned long calculate_board_ddr_clk(unsigned long dummy);
 #endif
 #define CONFIG_SYS_IMMR                CONFIG_SYS_CCSRBAR      /* PQII uses CONFIG_SYS_IMMR */
 
-#define CONFIG_SYS_PCIE3_ADDR          (CONFIG_SYS_CCSRBAR+0x8000)
-#define CONFIG_SYS_PCIE2_ADDR          (CONFIG_SYS_CCSRBAR+0x9000)
-#define CONFIG_SYS_PCIE1_ADDR          (CONFIG_SYS_CCSRBAR+0xa000)
-
 /* DDR Setup */
 #define CONFIG_VERY_BIG_RAM
+#ifdef CONFIG_MK_DDR2
+#define CONFIG_FSL_DDR2
+#else
 #define CONFIG_FSL_DDR3                1
+#endif
 #undef CONFIG_FSL_DDR_INTERACTIVE
 
 /* ECC will be enabled based on perf_mode environment variable */
@@ -119,6 +113,7 @@ extern unsigned long calculate_board_ddr_clk(unsigned long dummy);
 #define CONFIG_CHIP_SELECTS_PER_CTRL   2
 
 /* I2C addresses of SPD EEPROMs */
+#define CONFIG_DDR_SPD
 #define CONFIG_SYS_SPD_BUS_NUM         0       /* SPD EEPROM located on I2C bus 0 */
 #define SPD_EEPROM_ADDRESS1    0x51    /* CTLR 0 DIMM 0 */
 
@@ -238,6 +233,7 @@ extern unsigned long calculate_board_ddr_clk(unsigned long dummy);
 
 #define CONFIG_BOARD_EARLY_INIT_R      /* call board_early_init_r function */
 
+#define CONFIG_HWCONFIG                        /* enable hwconfig */
 #define CONFIG_FSL_NGPIXIS             /* use common ngPIXIS code */
 
 #ifdef CONFIG_FSL_NGPIXIS
@@ -259,6 +255,18 @@ extern unsigned long calculate_board_ddr_clk(unsigned long dummy);
 
 #define CONFIG_SYS_INIT_RAM_LOCK       1
 #define CONFIG_SYS_INIT_RAM_ADDR       0xffd00000      /* Initial L1 address */
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
+/* The assembler doesn't like typecast */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
+       ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
+         CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
+#else
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS  CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
+#endif
 #define CONFIG_SYS_INIT_RAM_END        0x00004000      /* End of used area in RAM */
 
 #define CONFIG_SYS_GBL_DATA_SIZE       128     /* num bytes initial data */
@@ -553,6 +561,7 @@ extern unsigned long calculate_board_ddr_clk(unsigned long dummy);
 #define CONFIG_CMD_ELF
 #define CONFIG_CMD_IRQ
 #define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_REGINFO
 
 #if defined(CONFIG_PCI)
 #define CONFIG_CMD_PCI
@@ -576,7 +585,8 @@ extern unsigned long calculate_board_ddr_clk(unsigned long dummy);
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP                    /* undef to save memory */
-#define CONFIG_CMDLINE_EDITING         /* Command-line editing */
+#define CONFIG_CMDLINE_EDITING                 /* Command-line editing */
+#define CONFIG_AUTO_COMPLETE                   /* add autocompletion support */
 #define CONFIG_SYS_LOAD_ADDR   0x2000000       /* default load address */
 #define CONFIG_SYS_PROMPT      "=> "           /* Monitor Command Prompt */
 #if defined(CONFIG_CMD_KGDB)