Blackfin: bf518f-ezbrd: enable SST SPI flash driver

[u-boot] / include / configs / PMC440.h

diff --git a/include/configs/PMC440.h b/include/configs/PMC440.h
index 7219bb8ae1897257de9e3075a507fbbcc7c47c56..012ae798d18aec1dc381b9ebf23a0e15b1f0554a 100644 (file)
--- a/include/configs/PMC440.h
+++ b/include/configs/PMC440.h
@@ -219,8 +219,8 @@
 #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
 #define CONFIG_DDR_DATA_EYE    /* use DDR2 optimization        */
 #endif
-#define CFG_MEM_TOP_HIDE       (4 << 10) /* don't use last 4kbytes     */
-                                       /* 440EPx errata CHIP 11        */
+#define CONFIG_SYS_MEM_TOP_HIDE        (4 << 10) /* don't use last 4kbytes */
+                                                 /* 440EPx errata CHIP 11 */
 
 /*-----------------------------------------------------------------------
  * I2C
@@ -230,7 +230,6 @@
 #define CONFIG_SYS_I2C_SPEED           400000  /* I2C speed and slave address  */
 #define CONFIG_SYS_I2C_SLAVE           0x7F
 
-#define CONFIG_I2C_CMD_TREE    1
 #define CONFIG_I2C_MULTI_BUS   1
 
 #define CONFIG_SYS_I2C_MULTI_EEPROMS
@@ -490,8 +489,8 @@
 #endif
 
 /* Memory Bank 1 (RESET) initialization */
-#define CFG_EBC_PB1AP          0x7f817200 //0x03017200
-#define CFG_EBC_PB1CR          (CFG_RESET_BASE | 0x1c000)
+#define CONFIG_SYS_EBC_PB1AP           0x7f817200 /* 0x03017200 */
+#define CONFIG_SYS_EBC_PB1CR           (CONFIG_SYS_RESET_BASE | 0x1c000)
 
 /* Memory Bank 4 (FPGA / 32Bit) initialization */
 #define CONFIG_SYS_EBC_PB4AP           0x03840f40      /* BME=0,TWT=7,CSN=1,TH=7,RE=1,SOR=0,BEM=1 */
@@ -505,7 +504,6 @@
  * NAND FLASH
  *----------------------------------------------------------------------*/
 #define CONFIG_SYS_MAX_NAND_DEVICE     1
-#define NAND_MAX_CHIPS         1
 #define CONFIG_SYS_NAND_BASE           (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
 #define CONFIG_SYS_NAND_SELECT_DEVICE  1 /* nand driver supports mutipl. chips */
 #define CONFIG_SYS_NAND_QUIET_TEST     1