* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
*----------------------------------------------------------------------*/
-#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */
+#define CONFIG_SYS_MONITOR_LEN (~(TEXT_BASE) + 1)
#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserve 256 kB for malloc() */
#define CONFIG_PRAM 0 /* use pram variable to overwrite */
#define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000
#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */
#define CONFIG_SYS_FLASH_BASE 0xfc000000 /* start of FLASH */
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
#define CONFIG_SYS_NAND_ADDR 0xd0000000 /* NAND Flash */
#define CONFIG_SYS_OCM_BASE 0xe0010000 /* ocm */
#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_OCM_BASE
/*-----------------------------------------------------------------------
* DDR SDRAM
*----------------------------------------------------------------------*/
-#define CONFIG_SYS_MBYTES_SDRAM (256) /* 256MB */
#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */
#endif
-#define CFG_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */
- /* 440EPx errata CHIP 11 */
+#define CONFIG_SYS_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */
+ /* 440EPx errata CHIP 11 */
/*-----------------------------------------------------------------------
* I2C
*----------------------------------------------------------------------*/
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
#define CONFIG_SYS_I2C_SLAVE 0x7F
-#define CONFIG_I2C_CMD_TREE 1
#define CONFIG_I2C_MULTI_BUS 1
#define CONFIG_SYS_I2C_MULTI_EEPROMS
"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
"addmisc=setenv bootargs ${bootargs} mem=${mem}\0" \
"nandargs=setenv bootargs root=/dev/mtdblock6 rootfstype=jffs2 rw\0" \
- "nand_boot=run nandargs addip addtty addmisc;bootm ${kernel_addr}\0" \
"nand_boot_fdt=run nandargs addip addtty addmisc;" \
"bootm ${kernel_addr} - ${fdt_addr}\0" \
- "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
- "run nfsargs addip addtty addmisc;" \
- "bootm\0" \
"net_nfs_fdt=tftp ${kernel_addr_r} ${bootfile};" \
"tftp ${fdt_addr_r} ${fdt_file};" \
"run nfsargs addip addtty addmisc;" \
"fdt_addr_r=800000\0" \
"fpga=fpga loadb 0 ${fpga_addr}\0" \
"load=tftp 200000 /tftpboot/pmc440/u-boot.bin\0" \
- "update=protect off fffa0000 ffffffff;era fffa0000 ffffffff;" \
- "cp.b 200000 fffa0000 60000\0" \
+ "update=protect off fff90000 ffffffff;era fff90000 ffffffff;" \
+ "cp.b 200000 fff90000 70000\0" \
""
#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+#define CONFIG_PPC4xx_EMAC
#define CONFIG_IBM_EMAC4_V4 1
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */
#define CONFIG_CMD_BSP
#define CONFIG_CMD_DATE
-#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_DTT
-#define CONFIG_CMD_DIAG
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_ELF
#define CONFIG_CMD_FAT
#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IRQ
#define CONFIG_CMD_MII
#define CONFIG_CMD_NAND
#define CONFIG_CMD_NET
#define CONFIG_CMD_PING
#define CONFIG_CMD_USB
#define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_SDRAM
/* POST support */
#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
/* Board-specific PCI */
#define CONFIG_SYS_PCI_TARGET_INIT
#define CONFIG_SYS_PCI_MASTER_INIT
+#define CONFIG_SYS_PCI_BOARD_FIXUP_IRQ
/* PCI identification */
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
#define CONFIG_SYS_PCI_SUBSYS_ID_NONMONARCH 0x0441 /* PCI Device ID: Non-Monarch */
#define CONFIG_SYS_PCI_SUBSYS_ID_MONARCH 0x0440 /* PCI Device ID: Monarch */
+/* for weak __pci_target_init() */
+#define CONFIG_SYS_PCI_SUBSYS_ID CONFIG_SYS_PCI_SUBSYS_ID_MONARCH
#define CONFIG_SYS_PCI_CLASSCODE_NONMONARCH PCI_CLASS_PROCESSOR_POWERPC
#define CONFIG_SYS_PCI_CLASSCODE_MONARCH PCI_CLASS_BRIDGE_HOST
#endif
/* Memory Bank 1 (RESET) initialization */
-#define CFG_EBC_PB1AP 0x7f817200 //0x03017200
-#define CFG_EBC_PB1CR (CFG_RESET_BASE | 0x1c000)
+#define CONFIG_SYS_EBC_PB1AP 0x7f817200 /* 0x03017200 */
+#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_RESET_BASE | 0x1c000)
/* Memory Bank 4 (FPGA / 32Bit) initialization */
#define CONFIG_SYS_EBC_PB4AP 0x03840f40 /* BME=0,TWT=7,CSN=1,TH=7,RE=1,SOR=0,BEM=1 */
* NAND FLASH
*----------------------------------------------------------------------*/
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define NAND_MAX_CHIPS 1
#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
#define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
#define CONFIG_SYS_NAND_QUIET_TEST 1
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