* CONFIG_PPCHAMELEON_CLK_25
* CONFIG_PPCHAMELEON_CLK_33
*/
+#if (!defined(CONFIG_PPCHAMELEON_CLK_25) && !defined(CONFIG_PPCHAMELEON_CLK_33))
+#define CONFIG_PPCHAMELEON_CLK_33
+#endif
#if (defined(CONFIG_PPCHAMELEON_CLK_25) && defined(CONFIG_PPCHAMELEON_CLK_33))
#error "* Two external frequencies (SysClk) are defined! *"
#ifdef CONFIG_PPCHAMELEON_CLK_25
- #define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */
+# define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */
#elif (defined (CONFIG_PPCHAMELEON_CLK_33))
-#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
+# define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
#else
-#error "* External frequency (SysClk) not defined! *"
+# error "* External frequency (SysClk) not defined! *"
#endif
#define CONFIG_BAUDRATE 115200
/* Ethernet stuff */
#define CONFIG_ENV_OVERWRITE /* Let the user to change the Ethernet MAC addresses */
#define CONFIG_ETHADDR 00:50:c2:1e:af:fe
+#define CONFIG_HAS_ETH1
#define CONFIG_ETH1ADDR 00:50:c2:1e:af:fd
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CONFIG_MII 1 /* MII PHY management */
#ifndef CONFIG_EXT_PHY
-#define CONFIG_PHY_ADDR 0 /* EMAC0 PHY address */
-#define CONFIG_PHY1_ADDR 1 /* EMAC1 PHY address */
+#define CONFIG_PHY_ADDR 0 /* EMAC0 PHY address */
+#define CONFIG_PHY1_ADDR 1 /* EMAC1 PHY address */
#else
#define CONFIG_PHY_ADDR 2 /* PHY address */
#endif
#undef CONFIG_WATCHDOG /* watchdog disabled */
-#define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/
-#define CFG_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */
+#define CONFIG_RTC_M41T11 1 /* uses a M41T00 RTC */
+#define CFG_I2C_RTC_ADDR 0x68
+#define CFG_M41T11_BASE_YEAR 1900
#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */
#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
-
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
#define CFG_GPIO0_OSRH 0x40000550
#define CFG_GPIO0_OSRL 0x00000110
#define CFG_GPIO0_ISR1H 0x00000000
-/*#define CFG_GPIO0_ISR1L 0x15555445*/
+/*#define CFG_GPIO0_ISR1L 0x15555445*/
#define CFG_GPIO0_ISR1L 0x15555444
#define CFG_GPIO0_TSRH 0x00000000
#define CFG_GPIO0_TSRL 0x00000000
#define CONFIG_NO_SERIAL_EEPROM
-/*#undef CONFIG_NO_SERIAL_EEPROM*/
+
/*--------------------------------------------------------------------*/
+
#ifdef CONFIG_NO_SERIAL_EEPROM
/*
#define PLL_PCIDIV_3 0x00000002
#define PLL_PCIDIV_4 0x00000003
-
#ifdef CONFIG_PPCHAMELEON_CLK_25
/* CPU - PLB/SDRAM - EBC - OPB - PCI (assuming a 25.0 MHz input clock to the 405EP) */
#define PPCHAMELEON_PLLMR0_133_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \
#if (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_HI)
/* Model HI */
-#define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_333_111_37_55_55
-#define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_333_111_37_55_55
+#define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_333_111_37_55_55
+#define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_333_111_37_55_55
#define CFG_OPB_FREQ 55555555
/* Model ME */
#elif (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_ME)
-#define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_266_133_33_66_33
-#define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_266_133_33_66_33
+#define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_266_133_33_66_33
+#define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_266_133_33_66_33
#define CFG_OPB_FREQ 66666666
#else
/* Model BA (default) */
-#define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_133_133_33_66_33
-#define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_133_133_33_66_33
+#define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_133_133_33_66_33
+#define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_133_133_33_66_33
#define CFG_OPB_FREQ 66666666
#endif
-#endif
+#endif /* CONFIG_NO_SERIAL_EEPROM */
-#define CONFIG_JFFS2_NAND 0 /* jffs2 on nand support */
+#define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */
#define CONFIG_JFFS2_NAND_DEV 0 /* nand device jffs2 lives on */
#define CONFIG_JFFS2_NAND_OFF 0 /* start of jffs2 partition */
#define CONFIG_JFFS2_NAND_SIZE 2*1024*1024 /* size of jffs2 partition */