]> git.sur5r.net Git - u-boot/blobdiff - include/configs/QS823.h
ColdFire: Update FlexBus CS for MCF532x
[u-boot] / include / configs / QS823.h
index 235bc480c7fec6cd905944bfcffa8ca27f373311..3657feaf70350863edc9e4f1db83d0126a107fc4 100644 (file)
 #undef CONFIG_STATUS_LED               /* Status LED disabled */
 #undef CONFIG_CAN_DRIVER               /* CAN Driver support disabled */
 
-#define CONFIG_BOOTP_MASK      (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
 
 #undef CONFIG_MAC_PARTITION
 #undef CONFIG_DOS_PARTITION
 
 #define CONFIG_RTC_MPC8xx      /* use internal RTC of MPC8xx */
 
-#define CONFIG_COMMANDS                (CFG_CMD_BDI    | \
-       CFG_CMD_BOOTD   | \
-       CFG_CMD_CONSOLE | \
-       CFG_CMD_DATE    | \
-       CFG_CMD_ENV     | \
-       CFG_CMD_FLASH   | \
-       CFG_CMD_IMI     | \
-       CFG_CMD_IMMAP   | \
-       CFG_CMD_MEMORY  | \
-       CFG_CMD_NET     | \
-       CFG_CMD_RUN)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+
+/*
+ * Command line configuration.
+ */
+#define CONFIG_CMD_BDI
+#define CONFIG_CMD_BOOTD
+#define CONFIG_CMD_CONSOLE
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_IMI
+#define CONFIG_CMD_IMMAP
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_RUN
+
 
 /*-----------------------------------------------------------------------
  * Environment variable storage is in FLASH, one sector before U-boot
 #define CFG_HUSH_PARSER                1               /* use "hush" command parser */
 #define CFG_PROMPT_HUSH_PS2    "> "
 
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
 #define CFG_CBSIZE             1024            /* Console I/O Buffer Size */
 #else
 #define CFG_CBSIZE             256             /* Console I/O Buffer Size */
  * Cache Configuration
  */
 #define CFG_CACHELINE_SIZE     16              /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
 #define CFG_CACHELINE_SHIFT    4               /* log base 2 of the above value */
 #endif