]> git.sur5r.net Git - u-boot/blobdiff - include/configs/SIMPC8313.h
ppc4xx: Remove unreferenced file include/405_dimm.h
[u-boot] / include / configs / SIMPC8313.h
index b847ce85db8efed583ae7959ed9bb4659e005447..70b7489ab1c90f95d1c60dd14de74224e490795c 100644 (file)
@@ -37,6 +37,7 @@
 #define CONFIG_MPC8313                 1
 
 #define CONFIG_PCI
+#define CONFIG_FSL_ELBC                        1
 
 #define CONFIG_MISC_INIT_R
 
 /*
  * Local Bus LCRR and LBCR regs
  */
-#define CONFIG_SYS_LCRR                (LCRR_DBYP | LCRR_EADC_1 | LCRR_CLKDIV_2)
+#define CONFIG_SYS_LCRR_DBYP   LCRR_DBYP
+#define CONFIG_SYS_LCRR_EADC   LCRR_EADC_1
+#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
 #define CONFIG_SYS_LBC_LBCR    (0x00040000 /* TODO */ \
                                | (0xFF << LBCR_BMT_SHIFT) \
                                | 0xF ) /* 0x0004ff0f */
 #else
 #define CONFIG_SYS_NAND_BASE           0xE2800000
 #endif
+#define CONFIG_SYS_FPGA_BASE           0xFF000000
 
 #define CONFIG_SYS_MAX_NAND_DEVICE     1
 #define NAND_MAX_CHIPS                 1
 #define CONFIG_MTD_NAND_VERIFY_WRITE
 #define CONFIG_CMD_NAND                1
 #define CONFIG_NAND_FSL_ELBC           1
-#define CONFIG_SYS_64BIT_VSPRINTF      /* needed for nand_util.c */
 
 #define CONFIG_SYS_NAND_U_BOOT_SIZE    (512 << 10)
 #define CONFIG_SYS_NAND_U_BOOT_DST     0x00100000
 #define CONFIG_SYS_NAND_U_BOOT_START   0x00100100
 #define CONFIG_SYS_NAND_U_BOOT_RELOC   0x00010000
+#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)
 
 #define CONFIG_SYS_NAND_BR_PRELIM      ( CONFIG_SYS_NAND_BASE \
                                        | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM        CONFIG_SYS_LBLAWBAR0_PRELIM
 #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR0_PRELIM
 
+#define CONFIG_SYS_BR1_PRELIM          ( CONFIG_SYS_FPGA_BASE \
+                                       | BR_PS_16 \
+                                       | BR_MS_UPMA \
+                                       | BR_V )
+#define CONFIG_SYS_OR1_PRELIM          ( OR_AM_2MB \
+                                       | OR_UPM_BCTLD)
+
+#define CONFIG_SYS_LBLAWBAR1_PRELIM    CONFIG_SYS_FPGA_BASE
+#define CONFIG_SYS_LBLAWAR1_PRELIM     (LBLAWAR_EN | LBLAWAR_2MB)
+
 /*
  * JFFS2 configuration
  */
 #endif
 
 #define CONFIG_CMDLINE_EDITING         1
-
+#define CONFIG_AUTO_COMPLETE           /* add autocompletion support   */
 
 /*
  * Miscellaneous configurable options
                                | SICRH_ETSEC2_G        \
                                | SICRH_TSOBI1          \
                                | SICRH_TSOBI2 )
-#define CONFIG_SYS_SICRL       (SICRL_USBDR            \
+#define CONFIG_SYS_SICRL       ( SICRL_LBC             \
+                               | SICRL_USBDR_10        \
                                | SICRL_ETSEC2_A )
 
 #define CONFIG_SYS_HID0_INIT   0x000000000
-#define CONFIG_SYS_HID0_FINAL  (HID0_ENABLE_MACHINE_CHECK      \
-                               | HID0_ENABLE_DYNAMIC_POWER_MANAGMENT )
+#define CONFIG_SYS_HID0_FINAL  (HID0_ENABLE_MACHINE_CHECK | \
+                                HID0_ENABLE_INSTRUCTION_CACHE | \
+                                HID0_ENABLE_DYNAMIC_POWER_MANAGMENT )
 
 #define CONFIG_SYS_HID2                HID2_HBE