pci: Add ability to re-enumerate PCI buses

[u-boot] / include / configs / XPEDITE5370.h

diff --git a/include/configs/XPEDITE5370.h b/include/configs/XPEDITE5370.h
index 26b798b4d8a56eb32e17c18049c72a93c6141bca..73e3d52e8350d21d82c3c634b4353b8525acbe18 100644 (file)
--- a/include/configs/XPEDITE5370.h
+++ b/include/configs/XPEDITE5370.h
@@ -38,6 +38,10 @@
 #define CONFIG_SYS_BOARD_NAME  "XPedite5370"
 #define CONFIG_BOARD_EARLY_INIT_R      /* Call board_pre_init */
 
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE   0xfff80000
+#endif
+
 #define CONFIG_PCI             1       /* Enable PCI/PCIE */
 #define CONFIG_PCI_PNP         1       /* do pci plug-and-play */
 #define CONFIG_PCI_SCAN_SHOW   1       /* show pci devices on startup */
@@ -47,6 +51,14 @@
 #define CONFIG_SYS_PCI_64BIT   1       /* enable 64-bit PCI resources */
 #define CONFIG_FSL_PCIE_RESET  1       /* need PCIe reset errata */
 #define CONFIG_FSL_LAW         1       /* Use common FSL init code */
+#define CONFIG_FSL_ELBC                1
+
+/*
+ * Multicore config
+ */
+#define CONFIG_MP
+#define CONFIG_BPTR_VIRT_ADDR  0xee000000      /* virt boot page address */
+#define CONFIG_MPC8xxx_DISABLE_BPTR            /* Don't leave BPTR enabled */
 
 /*
  * DDR config
@@ -91,8 +103,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define CONFIG_SYS_CCSRBAR             0xef000000      /* relocated CCSRBAR */
 #define CONFIG_SYS_CCSRBAR_PHYS        CONFIG_SYS_CCSRBAR      /* physical addr of CCSRBAR */
 #define CONFIG_SYS_IMMR                CONFIG_SYS_CCSRBAR      /* PQII uses CONFIG_SYS_IMMR */
-#define CONFIG_SYS_PCIE1_ADDR          (CONFIG_SYS_CCSRBAR + 0xa000)
-#define CONFIG_SYS_PCIE2_ADDR          (CONFIG_SYS_CCSRBAR + 0x9000)
 
 /*
  * Diagnostics
@@ -109,6 +119,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
  * 0xe000_0000 0xe7ff_ffff     SRAM/SSRAM/L1 Cache     128M non-cacheable
  * 0xe800_0000 0xe87f_ffff     PCIe1 IO                8M non-cacheable
  * 0xe880_0000 0xe8ff_ffff     PCIe2 IO                8M non-cacheable
+ * 0xee00_0000 0xee00_ffff     Boot page translation   4K non-cacheable
  * 0xef00_0000 0xef0f_ffff     CCSR/IMMR               1M non-cacheable
  * 0xef80_0000 0xef8f_ffff     NAND Flash              1M non-cacheable
  * 0xf000_0000 0xf7ff_ffff     NOR Flash 2             128M non-cacheable
@@ -144,7 +155,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 #define CONFIG_SYS_FLASH_AUTOPROTECT_LIST      { {0xfff40000, 0xc0000}, \
                                                  {0xf7f40000, 0xc0000} }
-#define CONFIG_SYS_MONITOR_BASE        TEXT_BASE       /* start of monitor */
+#define CONFIG_SYS_MONITOR_BASE        CONFIG_SYS_TEXT_BASE    /* start of monitor */
 
 /*
  * Chip select configuration
@@ -236,9 +247,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define CONFIG_OF_BOARD_SETUP          1
 #define CONFIG_OF_STDOUT_VIA_ALIAS     1
 
-#define CONFIG_SYS_64BIT_VSPRINTF      1
-#define CONFIG_SYS_64BIT_STRTOUL       1
-
 /*
  * I2C
  */
@@ -326,18 +334,18 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
  * Memory space is mapped 1-1, but I/O space must start from 0.
  */
 /* PCIE1 - VPX P1 */
-#define CONFIG_SYS_PCIE1_MEM_BASE      0x80000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS      CONFIG_SYS_PCIE1_MEM_BASE
+#define CONFIG_SYS_PCIE1_MEM_BUS       0x80000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS      CONFIG_SYS_PCIE1_MEM_BUS
 #define CONFIG_SYS_PCIE1_MEM_SIZE      0x40000000      /* 1G */
-#define CONFIG_SYS_PCIE1_IO_BASE       0x00000000
+#define CONFIG_SYS_PCIE1_IO_BUS                0x00000000
 #define CONFIG_SYS_PCIE1_IO_PHYS       0xe8000000
 #define CONFIG_SYS_PCIE1_IO_SIZE       0x00800000      /* 8M */
 
 /* PCIE2 - PEX8518 */
-#define CONFIG_SYS_PCIE2_MEM_BASE      0xc0000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS      CONFIG_SYS_PCIE2_MEM_BASE
+#define CONFIG_SYS_PCIE2_MEM_BUS       0xc0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS      CONFIG_SYS_PCIE2_MEM_BUS
 #define CONFIG_SYS_PCIE2_MEM_SIZE      0x10000000      /* 256M */
-#define CONFIG_SYS_PCIE2_IO_BASE       0x00000000
+#define CONFIG_SYS_PCIE2_IO_BUS                0x00000000
 #define CONFIG_SYS_PCIE2_IO_PHYS       0xe8800000
 #define CONFIG_SYS_PCIE2_IO_SIZE       0x00800000      /* 8M */
 
@@ -388,9 +396,11 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define CONFIG_CMD_PCA953X
 #define CONFIG_CMD_PCA953X_INFO
 #define CONFIG_CMD_PCI
+#define CONFIG_CMD_PCI_ENUM
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_SAVEENV
 #define CONFIG_CMD_SNTP
+#define CONFIG_CMD_REGINFO
 
 /*
  * Miscellaneous configurable options
@@ -404,6 +414,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define CONFIG_SYS_BARGSIZE    CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 #define CONFIG_SYS_HZ          1000            /* decrementer freq: 1ms ticks */
 #define CONFIG_CMDLINE_EDITING 1               /* add command line history     */
+#define CONFIG_AUTO_COMPLETE   1               /* add autocompletion support */
 #define CONFIG_LOADADDR                0x1000000       /* default location for tftp and bootm */
 #define CONFIG_BOOTDELAY       3               /* -1 disables auto-boot */
 #define CONFIG_PANIC_HANG                      /* do not reset board on panic */
@@ -420,12 +431,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define CONFIG_SYS_BOOTMAPSZ   (16 << 20)      /* Initial Memory map for Linux*/
 #define CONFIG_SYS_BOOTM_LEN   (16 << 20)      /* Increase max gunzip size */
 
-/*
- * Boot Flags
- */
-#define BOOTFLAG_COLD          0x01            /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM          0x02            /* Software reboot */
-
 /*
  * Environment Configuration
  */