Merge branch 'master' of git://www.denx.de/git/u-boot-mpc83xx

[u-boot] / include / configs / ads5121.h

diff --git a/include/configs/ads5121.h b/include/configs/ads5121.h
index 81e7c1e4db693b38dd43576ff7a176db2d0ba102..4226529eb7ddee16bd78ce66f9919da72c0b1a6f 100644 (file)
--- a/include/configs/ads5121.h
+++ b/include/configs/ads5121.h
@@ -45,14 +45,25 @@
  */
 #define CONFIG_E300            1       /* E300 Family */
 #define CONFIG_MPC512X         1       /* MPC512X family */
+#define CONFIG_FSL_DIU_FB      1       /* FSL DIU */
+
+/* video */
+#undef CONFIG_VIDEO
+
+#if defined(CONFIG_VIDEO)
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#endif
 
 /* CONFIG_PCI is defined at config time */
 
 #define CFG_MPC512X_CLKIN      66000000        /* in Hz */
 
 #define CONFIG_BOARD_EARLY_INIT_F              /* call board_early_init_f() */
+#define CONFIG_MISC_INIT_R
 
 #define CFG_IMMR               0x80000000
+#define CFG_DIU_ADDR           (CFG_IMMR+0x2100)
 
 #define CFG_MEMTEST_START      0x00200000      /* memtest region */
 #define CFG_MEMTEST_END                0x00400000
@@ -127,28 +138,28 @@
 #define CFG_MICRON_OCD_DEFAULT 0x01010780
 
 /* DDR Priority Manager Configuration */
-#define CFG_MDDRCGRP_PM_CFG1   0x000777AA
-#define CFG_MDDRCGRP_PM_CFG2   0x00000055
-#define CFG_MDDRCGRP_HIPRIO_CFG        0x00000000
-#define CFG_MDDRCGRP_LUT0_MU    0x11111117
-#define CFG_MDDRCGRP_LUT0_ML   0x7777777A
-#define CFG_MDDRCGRP_LUT1_MU    0x4444EEEE
-#define CFG_MDDRCGRP_LUT1_ML   0xEEEEEEEE
-#define CFG_MDDRCGRP_LUT2_MU    0x44444444
+#define CFG_MDDRCGRP_PM_CFG1   0x00077777
+#define CFG_MDDRCGRP_PM_CFG2   0x00000000
+#define CFG_MDDRCGRP_HIPRIO_CFG        0x00000001
+#define CFG_MDDRCGRP_LUT0_MU   0xFFEEDDCC
+#define CFG_MDDRCGRP_LUT0_ML   0xBBAAAAAA
+#define CFG_MDDRCGRP_LUT1_MU   0x66666666
+#define CFG_MDDRCGRP_LUT1_ML   0x55555555
+#define CFG_MDDRCGRP_LUT2_MU   0x44444444
 #define CFG_MDDRCGRP_LUT2_ML   0x44444444
-#define CFG_MDDRCGRP_LUT3_MU    0x55555555
+#define CFG_MDDRCGRP_LUT3_MU   0x55555555
 #define CFG_MDDRCGRP_LUT3_ML   0x55555558
-#define CFG_MDDRCGRP_LUT4_MU    0x11111111
-#define CFG_MDDRCGRP_LUT4_ML   0x1111117C
-#define CFG_MDDRCGRP_LUT0_AU    0x33333377
-#define CFG_MDDRCGRP_LUT0_AL   0x7777EEEE
-#define CFG_MDDRCGRP_LUT1_AU    0x11111111
-#define CFG_MDDRCGRP_LUT1_AL   0x11111111
-#define CFG_MDDRCGRP_LUT2_AU    0x11111111
+#define CFG_MDDRCGRP_LUT4_MU   0x11111111
+#define CFG_MDDRCGRP_LUT4_ML   0x11111122
+#define CFG_MDDRCGRP_LUT0_AU   0xaaaaaaaa
+#define CFG_MDDRCGRP_LUT0_AL   0xaaaaaaaa
+#define CFG_MDDRCGRP_LUT1_AU   0x66666666
+#define CFG_MDDRCGRP_LUT1_AL   0x66666666
+#define CFG_MDDRCGRP_LUT2_AU   0x11111111
 #define CFG_MDDRCGRP_LUT2_AL   0x11111111
-#define CFG_MDDRCGRP_LUT3_AU    0x11111111
+#define CFG_MDDRCGRP_LUT3_AU   0x11111111
 #define CFG_MDDRCGRP_LUT3_AL   0x11111111
-#define CFG_MDDRCGRP_LUT4_AU    0x11111111
+#define CFG_MDDRCGRP_LUT4_AU   0x11111111
 #define CFG_MDDRCGRP_LUT4_AL   0x11111111
 
 /*
@@ -161,7 +172,7 @@
 #define CFG_FLASH_USE_BUFFER_WRITE
 
 #define CFG_MAX_FLASH_BANKS    1               /* number of banks */
-#define CFG_FLASH_BANKS_LIST   {CFG_FLASH_BASE}
+#define CFG_FLASH_BANKS_LIST   {CFG_FLASH_BASE}
 #define CFG_MAX_FLASH_SECT     256             /* max sectors per device */
 
 #undef CFG_FLASH_CHECKSUM
@@ -189,7 +200,11 @@
 
 #define CFG_MONITOR_BASE       TEXT_BASE               /* Start of monitor */
 #define CFG_MONITOR_LEN                (256 * 1024)            /* Reserve 256 kB for Mon */
-#define CFG_MALLOC_LEN         (512 * 1024)            /* Reserved for malloc */
+#ifdef CONFIG_FSL_DIU_FB
+#define CFG_MALLOC_LEN         (6 * 1024 * 1024)       /* Reserved for malloc */
+#else
+#define CFG_MALLOC_LEN         (512 * 1024)
+#endif
 
 /*
  * Serial Port
@@ -357,6 +372,8 @@
 #define CFG_HID0_FINAL HID0_ENABLE_MACHINE_CHECK
 #define CFG_HID2       HID2_HBE
 
+#define CONFIG_HIGH_BATS       1       /* High BATs supported */
+
 /*
  * Internal Definitions
  *