Fix timer code for ARM systems: make sure that udelay() does not

[u-boot] / include / configs / at91rm9200dk.h

diff --git a/include/configs/at91rm9200dk.h b/include/configs/at91rm9200dk.h
index fb8a6100b5761a2497a60f7e2e0e4ca1eede224c..d32ec34fc2a708431864581d910d8fbc4970240b 100644 (file)
--- a/include/configs/at91rm9200dk.h
+++ b/include/configs/at91rm9200dk.h
@@ -29,7 +29,7 @@
  * If we are developing, we might want to start armboot from ram
  * so we MUST NOT initialize critical regs like mem-timing ...
  */
-#define CONFIG_INIT_CRITICAL           /* undef for developing */
+#define CONFIG_INIT_CRITICAL
 
 /* ARM asynchronous clock */
 #define AT91C_MAIN_CLOCK       179712000       /* from 18.432 MHz crystal (18432000 / 4 * 39) */
@@ -44,6 +44,37 @@
 #define CONFIG_SETUP_MEMORY_TAGS 1
 #define CONFIG_INITRD_TAG      1
 
+#ifdef CONFIG_INIT_CRITICAL
+#define CFG_USE_MAIN_OSCILLATOR                1
+/* flash */
+#define MC_PUIA_VAL    0x00000000
+#define MC_PUP_VAL     0x00000000
+#define MC_PUER_VAL    0x00000000
+#define MC_ASR_VAL     0x00000000
+#define MC_AASR_VAL    0x00000000
+#define EBI_CFGR_VAL   0x00000000
+#define SMC2_CSR_VAL   0x00003284 /* 16bit, 2 TDF, 4 WS */
+
+/* clocks */
+#define PLLAR_VAL      0x20263E04 /* 179.712000 MHz for PCK */
+#define PLLBR_VAL      0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
+#define MCKR_VAL       0x00000202 /* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */
+
+/* sdram */
+#define PIOC_ASR_VAL   0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
+#define PIOC_BSR_VAL   0x00000000
+#define PIOC_PDR_VAL   0xFFFF0000
+#define EBI_CSA_VAL    0x00000002 /* CS1=SDRAM */
+#define SDRC_CR_VAL    0x2188c155 /* set up the SDRAM */
+#define SDRAM          0x20000000 /* address of the SDRAM */
+#define SDRAM1         0x20000080 /* address of the SDRAM */
+#define SDRAM_VAL      0x00000000 /* value written to SDRAM */
+#define SDRC_MR_VAL    0x00000002 /* Precharge All */
+#define SDRC_MR_VAL1   0x00000004 /* refresh */
+#define SDRC_MR_VAL2   0x00000003 /* Load Mode Register */
+#define SDRC_MR_VAL3   0x00000000 /* Normal Mode */
+#define SDRC_TR_VAL    0x000002E0 /* Write refresh rate */
+#endif /* CONFIG_INIT_CRITICAL */
 /*
  * Size of malloc() pool
  */
@@ -58,8 +89,9 @@
  * Hardware drivers
  */
 
-/* define one of these to choose the DBGU or USART1 as console */
+/* define one of these to choose the DBGU, USART0  or USART1 as console */
 #define CONFIG_DBGU
+#undef CONFIG_USART0
 #undef CONFIG_USART1
 
 #undef CONFIG_HWFLOW                   /* don't include RTS/CTS flow control support   */
@@ -145,16 +177,27 @@
 #define CFG_ENV_SIZE                   0x2000  /* 0x8000 */
 #else
 #define CFG_ENV_IS_IN_FLASH            1
-#define CFG_ENV_ADDR                   (PHYS_FLASH_1 + 0xe000)  /* 0x10000 */
+#ifdef CONFIG_INIT_CRITICAL
+#define CFG_ENV_ADDR                   (PHYS_FLASH_1 + 0x60000)  /* after u-boot.bin */
+#define CFG_ENV_SIZE                   0x10000 /* sectors are 64K here */
+#else
+#define CFG_ENV_ADDR                   (PHYS_FLASH_1 + 0xe000)  /* between boot.bin and u-boot.bin.gz */
 #define CFG_ENV_SIZE                   0x2000  /* 0x8000 */
-#endif
+#endif /* CONFIG_INIT_CRITICAL */
+#endif /* CFG_ENV_IS_IN_DATAFLASH */
 
 
 #define CFG_LOAD_ADDR          0x21000000  /* default load address */
 
+#ifdef CONFIG_INIT_CRITICAL
+#define CFG_BOOT_SIZE          0x00 /* 0 KBytes */
+#define CFG_U_BOOT_BASE                PHYS_FLASH_1
+#define CFG_U_BOOT_SIZE                0x60000 /* 384 KBytes */
+#else
 #define CFG_BOOT_SIZE          0x6000 /* 24 KBytes */
 #define CFG_U_BOOT_BASE                (PHYS_FLASH_1 + 0x10000)
 #define CFG_U_BOOT_SIZE                0x10000 /* 64 KBytes */
+#endif /* CONFIG_INIT_CRITICAL */
 
 #define CFG_BAUDRATE_TABLE     {115200 , 19200, 38400, 57600, 9600 }