fsl: refactor MPC8610 and MPC5121 DIU code to use existing bitmap and logo features

[u-boot] / include / configs / bf561-acvilon.h

diff --git a/include/configs/bf561-acvilon.h b/include/configs/bf561-acvilon.h
index 0be170c3ee8ed41e7e6e2ba8883aa7d684195c48..0c0204fbd79c76ce51c2e751c71b1c520befae8e 100644 (file)
--- a/include/configs/bf561-acvilon.h
+++ b/include/configs/bf561-acvilon.h
@@ -131,7 +131,6 @@
 #define CONFIG_ENV_SECT_SIZE           (1056 * 8)
 #define CONFIG_ENV_OFFSET                      ((16 + 256) * 1056)
 #define CONFIG_ENV_SIZE                                (8 * 1056)
-#define CONFIG_ENV_OFFSET_REDUND       (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
 
 
 /*
@@ -145,7 +144,6 @@
 
 #define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2))
 #define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 3))
-#define BFIN_NAND_READY     PF10
 #define BFIN_NAND_WRITE(addr, cmd) \
        do { \
                bfin_write8(addr, cmd); \
@@ -154,12 +152,7 @@
 
 #define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd)
 #define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd)
-#define NAND_PLAT_DEV_READY(chip)      (bfin_read_FIO0_FLAG_D() & BFIN_NAND_READY)
-#define NAND_PLAT_INIT() \
-       do { \
-               bfin_write_FIO0_DIR(bfin_read_FIO0_DIR() & ~BFIN_NAND_READY); \
-               bfin_write_FIO0_INEN(bfin_read_FIO0_INEN() | BFIN_NAND_READY); \
-       } while (0)
+#define NAND_PLAT_GPIO_DEV_READY       GPIO_PF10
 
 
 /*