Merge branch 'next' of ../custodians into next

[u-boot] / include / configs / canyonlands.h

diff --git a/include/configs/canyonlands.h b/include/configs/canyonlands.h
index 3dddccfe7e681bc51122c1677f31f484c6ac68ff..e2c58a51ab11760b00d4cc11aafe03b8f815b37d 100644 (file)
--- a/include/configs/canyonlands.h
+++ b/include/configs/canyonlands.h
@@ -77,6 +77,13 @@
 #define CONFIG_SYS_PCIE0_XCFGBASE      0xc3000000
 #define CONFIG_SYS_PCIE1_XCFGBASE      0xc3001000
 
+/*
+ * BCSR bits as defined in the Canyonlands board user manual.
+ */
+#define BCSR_USBCTRL_OTG_RST   0x32
+#define BCSR_USBCTRL_HOST_RST  0x01
+#define BCSR_SELECT_PCIE       0x10
+
 #define        CONFIG_SYS_PCIE0_UTLBASE        0xc08010000ULL  /* 36bit physical addr  */
 
 /* base address of inbound PCIe window */
@@ -104,6 +111,7 @@
 
 #define CONFIG_SYS_OCM_BASE            0xE3000000      /* OCM: 64k             */
 #define CONFIG_SYS_SRAM_BASE           0xE8000000      /* SRAM: 256k           */
+#define CONFIG_SYS_SRAM_SIZE           (256 << 10)
 #define CONFIG_SYS_LOCAL_CONF_REGS     0xEF000000
 
 #define CONFIG_SYS_PERIPHERAL_BASE     0xEF600000      /* internal peripherals */
@@ -417,6 +425,7 @@
 #define CONFIG_SYS_USB_OHCI_REGS_BASE  (CONFIG_SYS_AHB_BASE | 0xd0000)
 #define CONFIG_SYS_USB_OHCI_SLOT_NAME  "ppc440"
 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
+#define CONFIG_SYS_USB_OHCI_BOARD_INIT
 #endif
 
 /*
@@ -593,7 +602,7 @@
 #define CONFIG_SYS_EBC_PB1CR           (CONFIG_SYS_FPGA_BASE | 0x3a000) /* BAS=FPGA,BS=2MB,BU=R/W,BW=16bit*/
 #endif /* !defined(CONFIG_ARCHES) */
 
-#define CONFIG_SYS_EBC_CFG             0xB8400000              /*  EBC0_CFG */
+#define CONFIG_SYS_EBC_CFG             0xbfc00000
 
 /*
  * Arches doesn't use PerCS3 but GPIO43, so let's configure the GPIO