fsl: refactor MPC8610 and MPC5121 DIU code to use existing bitmap and logo features

[u-boot] / include / configs / canyonlands.h

diff --git a/include/configs/canyonlands.h b/include/configs/canyonlands.h
index d814012c415ee08e952e7397d8eff5b2f18bd902..e2c58a51ab11760b00d4cc11aafe03b8f815b37d 100644 (file)
--- a/include/configs/canyonlands.h
+++ b/include/configs/canyonlands.h
@@ -77,6 +77,13 @@
 #define CONFIG_SYS_PCIE0_XCFGBASE      0xc3000000
 #define CONFIG_SYS_PCIE1_XCFGBASE      0xc3001000
 
+/*
+ * BCSR bits as defined in the Canyonlands board user manual.
+ */
+#define BCSR_USBCTRL_OTG_RST   0x32
+#define BCSR_USBCTRL_HOST_RST  0x01
+#define BCSR_SELECT_PCIE       0x10
+
 #define        CONFIG_SYS_PCIE0_UTLBASE        0xc08010000ULL  /* 36bit physical addr  */
 
 /* base address of inbound PCIe window */
@@ -104,6 +111,7 @@
 
 #define CONFIG_SYS_OCM_BASE            0xE3000000      /* OCM: 64k             */
 #define CONFIG_SYS_SRAM_BASE           0xE8000000      /* SRAM: 256k           */
+#define CONFIG_SYS_SRAM_SIZE           (256 << 10)
 #define CONFIG_SYS_LOCAL_CONF_REGS     0xEF000000
 
 #define CONFIG_SYS_PERIPHERAL_BASE     0xEF600000      /* internal peripherals */
@@ -132,9 +140,11 @@
  */
 #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
 #define        CONFIG_ENV_IS_IN_FLASH  1       /* use FLASH for environment vars */
+#define CONFIG_SYS_NOR_CS              0       /* NOR chip connected to CSx */
 #define CONFIG_SYS_NAND_CS             3       /* NAND chip connected to CSx */
 #else
 #define        CONFIG_ENV_IS_IN_NAND   1       /* use NAND for environment vars  */
+#define CONFIG_SYS_NOR_CS              3       /* NOR chip connected to CSx */
 #define CONFIG_SYS_NAND_CS             0       /* NAND chip connected to CSx */
 #define CONFIG_ENV_IS_EMBEDDED 1       /* use embedded environment */
 #endif
@@ -328,6 +338,15 @@
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS      3
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS  10
 
+/* I2C bootstrap EEPROM */
+#if defined(CONFIG_ARCHES)
+#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR      0x54
+#else
+#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR      0x52
+#endif
+#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET    0
+#define CONFIG_4xx_CONFIG_BLOCKSIZE            16
+
 /* I2C SYSMON (LM75, AD7414 is almost compatible)                      */
 #define CONFIG_DTT_LM75                1               /* ON Semi's LM75       */
 #define CONFIG_DTT_AD7414      1               /* use AD7414           */
@@ -406,6 +425,7 @@
 #define CONFIG_SYS_USB_OHCI_REGS_BASE  (CONFIG_SYS_AHB_BASE | 0xd0000)
 #define CONFIG_SYS_USB_OHCI_SLOT_NAME  "ppc440"
 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
+#define CONFIG_SYS_USB_OHCI_BOARD_INIT
 #endif
 
 /*
@@ -440,6 +460,7 @@
 /*
  * Commands additional to the ones defined in amcc-common.h
  */
+#define CONFIG_CMD_CHIP_CONFIG
 #if defined(CONFIG_ARCHES)
 #define CONFIG_CMD_DTT
 #define CONFIG_CMD_PCI
@@ -451,6 +472,7 @@
 #define CONFIG_CMD_FAT
 #define CONFIG_CMD_NAND
 #define CONFIG_CMD_PCI
+#define CONFIG_CMD_SATA
 #define CONFIG_CMD_SDRAM
 #define CONFIG_CMD_SNTP
 #define CONFIG_CMD_USB
@@ -516,6 +538,19 @@
 #endif /* CONFIG_ARCHES */
 #endif /* CONFIG_460GT */
 
+/*
+ * SATA driver setup
+ */
+#ifdef CONFIG_CMD_SATA
+#define CONFIG_SATA_DWC
+#define CONFIG_LIBATA
+#define SATA_BASE_ADDR         0xe20d1000      /* PPC460EX SATA Base Address */
+#define SATA_DMA_REG_ADDR      0xe20d0800      /* PPC460EX SATA Base Address */
+#define CONFIG_SYS_SATA_MAX_DEVICE     1       /* SATA MAX DEVICE */
+/* Convert sectorsize to wordsize */
+#define ATA_SECTOR_WORDS (ATA_SECT_SIZE/2)
+#endif
+
 /*-----------------------------------------------------------------------
  * External Bus Controller (EBC) Setup
  *----------------------------------------------------------------------*/
@@ -567,7 +602,7 @@
 #define CONFIG_SYS_EBC_PB1CR           (CONFIG_SYS_FPGA_BASE | 0x3a000) /* BAS=FPGA,BS=2MB,BU=R/W,BW=16bit*/
 #endif /* !defined(CONFIG_ARCHES) */
 
-#define CONFIG_SYS_EBC_CFG             0xB8400000              /*  EBC0_CFG */
+#define CONFIG_SYS_EBC_CFG             0xbfc00000
 
 /*
  * Arches doesn't use PerCS3 but GPIO43, so let's configure the GPIO