]> git.sur5r.net Git - u-boot/blobdiff - include/configs/chromebook_link.h
sunxi: Enable pre-console buffer
[u-boot] / include / configs / chromebook_link.h
index c9d84e4f06294a043fa295393f20ff449a8123ee..7e6d239d13d207c334da837485fc906ecf4ac792 100644 (file)
 
 #include <configs/x86-common.h>
 
-#define CONFIG_SYS_CAR_ADDR                    0xff7e0000
-#define CONFIG_SYS_CAR_SIZE                    (128 * 1024)
+
 #define CONFIG_SYS_MONITOR_LEN                 (1 << 20)
+
 #define CONFIG_DCACHE_RAM_MRC_VAR_SIZE         0x4000
-#define CONFIG_SYS_X86_START16                 0xfffff800
 #define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_DISPLAY_CPUINFO
 
-#define CONFIG_X86_RESET_VECTOR
 #define CONFIG_NR_DRAM_BANKS                   8
 #define CONFIG_X86_MRC_ADDR                    0xfffa0000
 #define CONFIG_CACHE_MRC_SIZE_KB               512
 
-#define CONFIG_COREBOOT_SERIAL
+#define CONFIG_X86_SERIAL
 
 #define CONFIG_SCSI_DEV_LIST           {PCI_VENDOR_ID_INTEL, \
                        PCI_DEVICE_ID_INTEL_NM10_AHCI},       \
@@ -39,9 +36,8 @@
        {PCI_VENDOR_ID_INTEL,           \
                        PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE}
 
-#define CONFIG_X86_OPTION_ROM_FILENAME         pci8086,0166.bin
+#define CONFIG_X86_OPTION_ROM_FILE             pci8086,0166.bin
 #define CONFIG_X86_OPTION_ROM_ADDR             0xfff90000
-#define CONFIG_VIDEO_X86
 
 #define CONFIG_PCI_MEM_BUS     0xe0000000
 #define CONFIG_PCI_MEM_PHYS    CONFIG_PCI_MEM_BUS