#define CONFIG_MX6
#define CONFIG_SYS_LITTLE_ENDIAN
#define CONFIG_MACH_TYPE 4273
-#define CONFIG_SYS_HZ 1000
+
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_DM
+#define CONFIG_CMD_DM
+
+#define CONFIG_DM_GPIO
+#define CONFIG_CMD_GPIO
+
+#define CONFIG_DM_SERIAL
+#define CONFIG_SYS_MALLOC_F_LEN (1 << 10)
+#endif
/* Display information on boot */
#define CONFIG_DISPLAY_CPUINFO
#undef CONFIG_CMD_XIMG
#undef CONFIG_CMD_FPGA
#undef CONFIG_CMD_IMLS
-#undef CONFIG_CMD_NET
-#undef CONFIG_CMD_NFS
/* MMC */
#define CONFIG_MMC
"mmcboot=echo Booting from mmc ...; " \
"run mmcargs; " \
"run doboot\0" \
+ "satadev=0\0" \
+ "sataroot=/dev/sda2 rw rootwait\0" \
+ "sataargs=setenv bootargs console=${console} " \
+ "root=${sataroot} " \
+ "${video}\0" \
+ "loadsatabootscript=load sata ${satadev} ${loadaddr} ${bootscr}\0" \
+ "satabootscript=echo Running bootscript from sata ...; " \
+ "source ${loadaddr}\0" \
+ "sataloadkernel=load sata ${satadev} ${loadaddr} ${kernel}\0" \
+ "sataloadfdt=load sata ${satadev} ${fdtaddr} ${fdtfile}\0" \
+ "sataboot=echo Booting from sata ...; "\
+ "run sataargs; " \
+ "run doboot\0" \
+ "nandroot=/dev/mtdblock4 rw\0" \
+ "nandrootfstype=ubifs\0" \
+ "nandargs=setenv bootargs console=${console} " \
+ "root=${nandroot} " \
+ "rootfstype=${nandrootfstype} " \
+ "${video}\0" \
+ "nandloadfdt=nand read ${fdtaddr} 780000 80000;\0" \
+ "nandboot=echo Booting from nand ...; " \
+ "run nandargs; " \
+ "nand read ${loadaddr} 0 780000; " \
+ "if ${loadfdt}; then " \
+ "run nandloadfdt;" \
+ "fi; " \
+ "run doboot\0" \
"boot=mmc dev ${mmcdev}; " \
"if mmc rescan; then " \
"if run loadmmcbootscript; then " \
"run mmcboot;" \
"fi;" \
"fi;" \
- "fi;\0"
+ "fi;" \
+ "if sata init; then " \
+ "if run loadsatabootscript; then " \
+ "run satabootscript;" \
+ "else "\
+ "if run sataloadkernel; then " \
+ "if ${loadfdt}; then " \
+ "run sataloadfdt; " \
+ "fi;" \
+ "run sataboot;" \
+ "fi;" \
+ "fi;" \
+ "fi;" \
+ "run nandboot\0"
#define CONFIG_BOOTCOMMAND \
"run setboottypem; run boot"
#define CONFIG_SPI_FLASH_SST
#define CONFIG_SPI_FLASH_WINBOND
+/* NAND */
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_CMD_NAND
+#define CONFIG_SYS_NAND_BASE 0x40000000
+#define CONFIG_SYS_NAND_MAX_CHIPS 1
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_NAND_MXS
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+/* APBH DMA is required for NAND support */
+#define CONFIG_APBH_DMA
+#define CONFIG_APBH_DMA_BURST
+#define CONFIG_APBH_DMA_BURST8
+#endif
+
+/* Ethernet */
+#define CONFIG_FEC_MXC
+#define CONFIG_FEC_MXC_PHYADDR 0
+#define CONFIG_FEC_XCV_TYPE RGMII
+#define IMX_FEC_BASE ENET_BASE_ADDR
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_ATHEROS
+#define CONFIG_MII
+#define CONFIG_ETHPRIME "FEC0"
+#define CONFIG_ARP_TIMEOUT 200UL
+#define CONFIG_NET_RETRY_COUNT 5
+
+/* USB */
+#define CONFIG_CMD_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_MX6
+#define CONFIG_USB_STORAGE
+#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS 0
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */
+
+/* I2C */
+#define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_SPEED 100000
+#define CONFIG_SYS_MXC_I2C3_SPEED 400000
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_I2C_EEPROM_BUS 2
+
+/* SATA */
+#define CONFIG_CMD_SATA
+#define CONFIG_SYS_SATA_MAX_DEVICE 1
+#define CONFIG_LIBATA
+#define CONFIG_LBA48
+#define CONFIG_DWC_AHSATA
+#define CONFIG_DWC_AHSATA_PORT_ID 0
+#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
+
/* GPIO */
#define CONFIG_MXC_GPIO
#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+#define CONFIG_SERIAL_TAG
/* misc */
#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_STACKSIZE (128 * 1024)
#define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024)
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 800 /* 400 KB */
+#define CONFIG_OF_BOARD_SETUP
/* SPL */
#include "imx6_spl.h"