Merge with /home/sr/git/u-boot

[u-boot] / include / configs / cmc_pu2.h

diff --git a/include/configs/cmc_pu2.h b/include/configs/cmc_pu2.h
index 12d0cca265be8a170daedbcc871fe58d6a561ca3..9ed538b110284310527597c98b2b0158f80b2854 100644 (file)
--- a/include/configs/cmc_pu2.h
+++ b/include/configs/cmc_pu2.h
@@ -26,14 +26,13 @@
 #define __CONFIG_H
 
 /* ARM asynchronous clock */
-#define AT91C_MAIN_CLOCK       207360000       /* from 18.432 MHz crystal (18432000 / 4 * 45) */
+#define AT91C_MAIN_CLOCK       179712000       /* from 18.432 MHz crystal (18432000 / 4 * 39) */
 #define AT91C_MASTER_CLOCK     (AT91C_MAIN_CLOCK/3)    /* peripheral clock */
 
 #define AT91_SLOW_CLOCK                32768   /* slow clock */
 
 #define CONFIG_ARM920T         1       /* This is an ARM920T Core      */
 #define CONFIG_AT91RM9200      1       /* It's an Atmel AT91RM9200 SoC */
-#define CONFIG_AT91RM9200DK    1       /* on an AT91RM9200DK Board     */
 #define CONFIG_CMC_PU2         1       /* on an CMC_PU2 Board          */
 #undef  CONFIG_USE_IRQ                 /* we don't need IRQ/FIQ stuff  */
 #define USE_920T_MMU           1
@@ -54,7 +53,7 @@
 #define SMC2_CSR_VAL   0x100032ad /* 16bit, 2 TDF, 4 WS */
 
 /* clocks */
-#define PLLAR_VAL      0x202CBE04 /* 207.360 MHz for PCK */
+#define PLLAR_VAL      0x2026BE04 /* 179,712 MHz for PCK */
 #define PLLBR_VAL      0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
 #define MCKR_VAL       0x00000202 /* PCK/3 = MCK Master Clock = 69.120MHz from PLLA */