rockchip: rk3288: use spl_early_init() instead of spl_init()

[u-boot] / include / configs / corenet_ds.h

diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h
index 7637bb8777ce7d839fa18487450e5de32f7d03ea..f810d34848f8d4697055f19f6faad5af1f511fd0 100644 (file)
--- a/include/configs/corenet_ds.h
+++ b/include/configs/corenet_ds.h
@@ -42,7 +42,6 @@
 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
                (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
-#define CONFIG_SYS_NO_FLASH
 #endif
 
 /* High Level Configuration Options */
@@ -59,8 +58,6 @@
 
 #define CONFIG_SYS_FSL_CPC             /* Corenet Platform Cache */
 #define CONFIG_SYS_NUM_CPC             CONFIG_SYS_NUM_DDR_CTLRS
-#define CONFIG_FSL_ELBC                        /* Has Enhanced localbus controller */
-#define CONFIG_FSL_CAAM                        /* Enable SEC/CAAM */
 #define CONFIG_PCIE1                   /* PCIE controller 1 */
 #define CONFIG_PCIE2                   /* PCIE controller 2 */
 #define CONFIG_FSL_PCI_INIT            /* Use common FSL init code */
@@ -68,7 +65,7 @@
 
 #define CONFIG_ENV_OVERWRITE
 
-#ifdef CONFIG_SYS_NO_FLASH
+#ifndef CONFIG_MTD_NOR_FLASH
 #if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL)
 #define CONFIG_ENV_IS_NOWHERE
 #endif