]> git.sur5r.net Git - u-boot/blobdiff - include/configs/da850evm.h
Merge branch 'master' of git://git.denx.de/u-boot-video
[u-boot] / include / configs / da850evm.h
index e4cc3be998fc914d61f94a61cdf7c2c8fb18ffe8..09a966092962c90d35095b67d2bb2e02f548b939 100644 (file)
  * Board
  */
 #define CONFIG_DRIVER_TI_EMAC
+/* check if direct NOR boot config is used */
+#ifndef CONFIG_DIRECT_NOR_BOOT
 #define CONFIG_USE_SPIFLASH
+#endif
 
 
 /*
 #define CONFIG_SYS_TIMERBASE           DAVINCI_TIMER0_BASE
 #define CONFIG_SYS_HZ_CLOCK            clk_get(DAVINCI_AUXCLK_CLKID)
 #define CONFIG_SYS_HZ                  1000
-#define CONFIG_SYS_TEXT_BASE           0xc1080000
 #define CONFIG_SYS_DA850_PLL_INIT
 #define CONFIG_SYS_DA850_DDR_INIT
 
+#ifdef CONFIG_DIRECT_NOR_BOOT
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_DA8XX_GPIO
+#define CONFIG_SYS_TEXT_BASE           0x60000000
+#define CONFIG_SYS_DV_NOR_BOOT_CFG     (0x11)
+#define CONFIG_DA850_LOWLEVEL
+#else
+#define CONFIG_SYS_TEXT_BASE           0xc1080000
+#endif
+
 /*
  * Memory Info
  */
@@ -62,7 +74,6 @@
 #define CONFIG_SYS_MEMTEST_END         (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024)
 
 #define CONFIG_NR_DRAM_BANKS   1 /* we have 1 bank of DRAM */
-#define CONFIG_STACKSIZE       (256*1024) /* regular stack */
 
 #define CONFIG_SYS_DA850_SYSCFG_SUSPSRC (      \
        DAVINCI_SYSCFG_SUSPSRC_TIMER0 |         \
 #define CONFIG_SYS_ALE_MASK            0x8
 #undef CONFIG_SYS_NAND_HW_ECC
 #define CONFIG_SYS_MAX_NAND_DEVICE     1 /* Max number of NAND devices */
+#define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_SIZE      (2 << 10)
+#define CONFIG_SYS_NAND_BLOCK_SIZE     (128 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_OFFS    0x28000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE    0x60000
+#define CONFIG_SYS_NAND_U_BOOT_DST     0xc1080000
+#define CONFIG_SYS_NAND_U_BOOT_START   CONFIG_SYS_NAND_U_BOOT_DST
+#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP        (CONFIG_SYS_NAND_U_BOOT_DST - \
+                                       CONFIG_SYS_NAND_U_BOOT_SIZE - \
+                                       CONFIG_SYS_MALLOC_LEN -       \
+                                       GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_NAND_ECCPOS         {                               \
+                               24, 25, 26, 27, 28, \
+                               29, 30, 31, 32, 33, 34, 35, 36, 37, 38, \
+                               39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \
+                               49, 50, 51, 52, 53, 54, 55, 56, 57, 58, \
+                               59, 60, 61, 62, 63 }
+#define CONFIG_SYS_NAND_PAGE_COUNT     64
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS  0
+#define CONFIG_SYS_NAND_ECCSIZE                512
+#define CONFIG_SYS_NAND_ECCBYTES       10
+#define CONFIG_SYS_NAND_OOBSIZE                64
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_SIMPLE
+#define CONFIG_SPL_NAND_LOAD
 #endif
 
 /*
 #define CONFIG_CMD_MMC
 #endif
 
+#ifndef CONFIG_DIRECT_NOR_BOOT
 /* defines for SPL */
 #define CONFIG_SPL
 #define CONFIG_SPL_SERIAL_SUPPORT
 #define CONFIG_SPL_STACK       0x8001ff00
 #define CONFIG_SPL_TEXT_BASE   0x80000000
 #define CONFIG_SPL_MAX_SIZE    32768
-
+#endif
 
 /* Load U-Boot Image From MMC */
 #ifdef CONFIG_SPL_MMC_LOAD
 
 /* additions for new relocation code, must added to all boards */
 #define CONFIG_SYS_SDRAM_BASE          0xc0000000
+
+#ifdef CONFIG_DIRECT_NOR_BOOT
+#define CONFIG_SYS_INIT_SP_ADDR                0x8001ff00
+#else
 #define CONFIG_SYS_INIT_SP_ADDR                (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
                                        GENERATED_GBL_DATA_SIZE)
+#endif /* CONFIG_DIRECT_NOR_BOOT */
 #endif /* __CONFIG_H */