Merge with git://git.kernel.org/pub/scm/boot/u-boot/u-boot.git#mpc83xx

[u-boot] / include / configs / delta.h

diff --git a/include/configs/delta.h b/include/configs/delta.h
index ac412ee8783ee5bb9f3a5007674cab4a3443928d..b42a7e2c1aec9dd7ffae5a430db455a7bd149712 100644 (file)
--- a/include/configs/delta.h
+++ b/include/configs/delta.h
@@ -43,7 +43,7 @@
 /*
  * Size of malloc() pool
  */
-#define CFG_MALLOC_LEN     (CFG_ENV_SIZE + 128*1024)
+#define CFG_MALLOC_LEN     (CFG_ENV_SIZE + 256*1024)
 #define CFG_GBL_DATA_SIZE      128     /* size in bytes reserved for initial data */
 
 /*
@@ -73,9 +73,8 @@
 #ifdef TURN_ON_ETHERNET
 # define CONFIG_COMMANDS        (CONFIG_CMD_DFL | CFG_CMD_PING)
 #else
-# define CONFIG_COMMANDS       ((CONFIG_CMD_DFL | CFG_CMD_NAND) \
-                               & ~(CFG_CMD_NET | CFG_CMD_FLASH | \
-                                   CFG_CMD_ENV | CFG_CMD_IMLS))
+# define CONFIG_COMMANDS       ((CONFIG_CMD_DFL | CFG_CMD_ENV | CFG_CMD_NAND) \
+                               & ~(CFG_CMD_NET | CFG_CMD_FLASH | CFG_CMD_IMLS))
 #endif
 
 
@@ -157,22 +156,49 @@
 #define CFG_DRAM_BASE          0xa0000000 /* at CS0 */
 #define CFG_DRAM_SIZE          0x04000000 /* 64 MB Ram */
 
-#define CFG_SKIP_DRAM_SCRUB    1
+#undef CFG_SKIP_DRAM_SCRUB
 
 /*
  * NAND Flash
  */
 /* Use the new NAND code. (BOARDLIBS = drivers/nand/libnand.a required) */
 #define CONFIG_NEW_NAND_CODE
-#define CFG_NAND0_BASE         0x43100040 /* 0x10000000 */
+#define CFG_NAND0_BASE         0x0 /* 0x43100040 */ /* 0x10000000 */
 #undef CFG_NAND1_BASE
 
 #define CFG_NAND_BASE_LIST     { CFG_NAND0_BASE }
 #define CFG_MAX_NAND_DEVICE    1       /* Max number of NAND devices */
 #define SECTORSIZE             512
-/* #define NAND_NO_RB */
 #define NAND_DELAY_US          25      /* mk@tbd: could be 0, I guess */
 
+/* nand timeout values */
+#define CFG_NAND_PROG_ERASE_TO 3000
+#define CFG_NAND_OTHER_TO      100
+#define CFG_NAND_SENDCMD_RETRY 3
+#undef NAND_ALLOW_ERASE_ALL    /* Allow erasing bad blocks - don't use */
+
+/* NAND Timing Parameters (in ns) */
+#define NAND_TIMING_tCH        10
+#define NAND_TIMING_tCS        0
+#define NAND_TIMING_tWH                20
+#define NAND_TIMING_tWP        40
+
+#define NAND_TIMING_tRH        20
+#define NAND_TIMING_tRP        40
+
+#define NAND_TIMING_tR         11123
+/* #define NAND_TIMING_tWHR    110 */
+#define NAND_TIMING_tWHR       100
+#define NAND_TIMING_tAR                10
+
+/* NAND debugging */
+#define CFG_DFC_DEBUG1 /* usefull */
+#undef CFG_DFC_DEBUG2  /* noisy */
+#undef CFG_DFC_DEBUG3  /* extremly noisy  */
+
+#define CONFIG_MTD_DEBUG
+#define CONFIG_MTD_DEBUG_VERBOSE 1
+
 #define ADDR_COLUMN 1
 #define ADDR_PAGE 2
 #define ADDR_COLUMN_PAGE 3
@@ -253,8 +279,8 @@
 #define        CFG_MONITOR_LEN         PHYS_FLASH_SECT_SIZE
 #endif /* #ifndef CFG_NO_FLASH */
 
-#define CFG_ENV_IS_NOWHERE
-/* #define CFG_ENV_IS_IN_NAND      1 */
+/* #define CFG_ENV_IS_NOWHERE */
+#define CFG_ENV_IS_IN_NAND     1
 #define CFG_ENV_OFFSET         0x40000
 #define CFG_ENV_SIZE           0x4000