microblaze: Enable TFTP put command

[u-boot] / include / configs / devkit8000.h

diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h
index 3ea453250007b293542c969b88f428d7a4ef980d..2b6a6ee091815a36162f7d601d0a71aaa28b8ff4 100644 (file)
--- a/include/configs/devkit8000.h
+++ b/include/configs/devkit8000.h
@@ -36,7 +36,13 @@
 #define CONFIG_OMAP34XX                1       /* which is a 34XX */
 #define CONFIG_OMAP3_DEVKIT8000        1       /* working with DevKit8000 */
 
-#define        CONFIG_SYS_TEXT_BASE    0x80008000
+/*
+ * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
+ * 64 bytes before this address should be set aside for u-boot.img's
+ * header. That is 0x800FFFC0--0x80100000 should not be used for any
+ * other needs.
+ */
+#define CONFIG_SYS_TEXT_BASE   0x80100000
 
 #define CONFIG_SDRC    /* The chip has SDRC controller */
 
@@ -67,10 +73,6 @@
 #define CONFIG_SYS_MALLOC_LEN          (CONFIG_ENV_SIZE + (128 << 10))
 
 /* Hardware drivers */
-
-/* DDR - I use Micron DDR */
-#define CONFIG_OMAP3_MICRON_DDR                1
-
 /* DM9000 */
 #define CONFIG_NET_RETRY_COUNT         20
 #define        CONFIG_DRIVER_DM9000            1
@@ -279,7 +281,6 @@
 /*  Physical Memory Map  */
 #define CONFIG_NR_DRAM_BANKS           2 /* CS1 may or may not be populated */
 #define PHYS_SDRAM_1                   OMAP34XX_SDRC_CS0
-#define PHYS_SDRAM_1_SIZE              (128 << 20)     /* at least 128 MiB */
 #define PHYS_SDRAM_2                   OMAP34XX_SDRC_CS1
 
 /* NAND and environment organization  */
@@ -309,6 +310,7 @@
 
 #define CONFIG_SPL_LIBCOMMON_SUPPORT
 #define CONFIG_SPL_LIBDISK_SUPPORT
+#define CONFIG_SPL_BOARD_INIT
 #define CONFIG_SPL_I2C_SUPPORT
 #define CONFIG_SPL_LIBGENERIC_SUPPORT
 #define CONFIG_SPL_SERIAL_SUPPORT
@@ -341,17 +343,12 @@
 #define CONFIG_SYS_NAND_ECCSIZE                512
 #define CONFIG_SYS_NAND_ECCBYTES       3
 
-#define CONFIG_SYS_NAND_ECCSTEPS       (CONFIG_SYS_NAND_PAGE_SIZE / \
-                                               CONFIG_SYS_NAND_ECCSIZE)
-#define CONFIG_SYS_NAND_ECCTOTAL       (CONFIG_SYS_NAND_ECCBYTES * \
-                                               CONFIG_SYS_NAND_ECCSTEPS)
-
 #define CONFIG_SYS_NAND_U_BOOT_START   CONFIG_SYS_TEXT_BASE
 
 #define CONFIG_SYS_NAND_U_BOOT_OFFS    0x80000
 #define CONFIG_SYS_NAND_U_BOOT_SIZE    0x200000
 
-#define CONFIG_SYS_SPL_MALLOC_START    0x80108000
+#define CONFIG_SYS_SPL_MALLOC_START    0x80208000
 #define CONFIG_SYS_SPL_MALLOC_SIZE     0x100000        /* 1 MB */
 
 #endif /* __CONFIG_H */