fsl: refactor MPC8610 and MPC5121 DIU code to use existing bitmap and logo features

[u-boot] / include / configs / eNET.h

diff --git a/include/configs/eNET.h b/include/configs/eNET.h
index 05d7db87b7f99e8b075aa7044d237a43c463f54b..361fe61b04fdbef4e75cefe20ae6877b2cc8f04d 100644 (file)
--- a/include/configs/eNET.h
+++ b/include/configs/eNET.h
@@ -53,7 +53,7 @@
  * bottom (processor) board MUST be removed!
  */
 #undef CONFIG_WATCHDOG
-#undef CONFIG_HW_WATCHDOG
+#define CONFIG_HW_WATCHDOG
 
  /*-----------------------------------------------------------------------
   * Serial Configuration
@@ -105,9 +105,10 @@
 #define CONFIG_CMD_LOADS       /* loads                        */
 #define CONFIG_CMD_MEMORY      /* md mm nm mw cp cmp crc base loop mtest */
 #define CONFIG_CMD_MISC                /* Misc functions like sleep etc*/
-#undef CONFIG_CMD_NET          /* bootp, tftpboot, rarpboot    */
+#define CONFIG_CMD_NET         /* bootp, tftpboot, rarpboot    */
 #undef CONFIG_CMD_NFS          /* NFS support                  */
 #define CONFIG_CMD_PCI         /* PCI support                  */
+#define CONFIG_CMD_PING                /* ICMP echo support            */
 #define CONFIG_CMD_RUN         /* run command in env variable  */
 #define CONFIG_CMD_SAVEENV     /* saveenv                      */
 #define CONFIG_CMD_SETGETDCR   /* DCR support on 4xx           */
@@ -140,7 +141,7 @@
 
 #define        CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address */
 
-#define        CONFIG_SYS_HZ                   1024            /* incrementer freq: 1kHz */
+#define        CONFIG_SYS_HZ                   1000            /* incrementer freq: 1kHz */
 
 /*-----------------------------------------------------------------------
  * SDRAM Configuration
@@ -159,7 +160,7 @@
  * CPU Features
  */
 #define CONFIG_SYS_SC520_HIGH_SPEED    0       /* 100 or 133MHz */
-#undef  CONFIG_SYS_SC520_RESET                 /* use SC520 MMCR's to reset cpu */
+#define CONFIG_SYS_SC520_RESET                 /* use SC520 MMCR's to reset cpu */
 #define CONFIG_SYS_SC520_TIMER                 /* use SC520 swtimers */
 #undef  CONFIG_SYS_GENERIC_TIMER               /* use the i8254 PIT timers */
 #undef  CONFIG_SYS_TSC_TIMER                   /* use the Pentium TSC timers */
@@ -198,7 +199,7 @@
                                         CONFIG_SYS_FLASH_BASE_1, \
                                         CONFIG_SYS_FLASH_BASE_2}
 #define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 #define CONFIG_SYS_MAX_FLASH_SECT      128     /* max number of sectors on one chip */
 #define CONFIG_SYS_FLASH_CFI_WIDTH     FLASH_CFI_8BIT
 #define CONFIG_SYS_FLASH_LEGACY_512Kx8
@@ -226,13 +227,11 @@
 #define CONFIG_SYS_THIRD_PCI_IRQ   11
 #define CONFIG_SYS_FORTH_PCI_IRQ   15
 
-/*-----------------------------------------------------------------------
- * Hardware watchdog configuration
+ /*
+ * Network device (TRL8100B) support
  */
-#define CONFIG_SYS_WATCHDOG_PIO_BIT            0x8000
-#define CONFIG_SYS_WATCHDIG_PIO_DATA           SC520_PIODATA15_0
-#define CONFIG_SYS_WATCHDIG_PIO_CLR            SC520_PIOCLR15_0
-#define CONFIG_SYS_WATCHDIG_PIO_SET            SC520_PIOSET15_0
+#define CONFIG_NET_MULTI
+#define CONFIG_RTL8139
 
 /*-----------------------------------------------------------------------
  * FPGA configuration