85xx boards: Rename CONFIG_DDR_DLL to CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN

[u-boot] / include / configs / eNET.h

diff --git a/include/configs/eNET.h b/include/configs/eNET.h
index 61897949dd93f33e310048363ba503ff70e26111..78cab29e8c8526548665e75103d89f8fdfafc45e 100644 (file)
--- a/include/configs/eNET.h
+++ b/include/configs/eNET.h
@@ -29,8 +29,6 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#define CONFIG_RELOC_FIXUP_WORKS
-
 /*
  * Stuff still to be dealt with -
  */
@@ -53,13 +51,12 @@
  * bottom (processor) board MUST be removed!
  */
 #undef CONFIG_WATCHDOG
-#undef CONFIG_HW_WATCHDOG
+#define CONFIG_HW_WATCHDOG
 
  /*-----------------------------------------------------------------------
   * Serial Configuration
   */
 #define CONFIG_SERIAL_MULTI
-#undef CONFIG_SERIAL_SOFTWARE_FIFO
 #define CONFIG_CONS_INDEX              1
 #define CONFIG_SYS_NS16550
 #define CONFIG_SYS_NS16550_SERIAL
@@ -175,7 +172,7 @@
 #define CONFIG_SYS_STACK_SIZE          0x8000          /* Size of bootloader stack */
 #define CONFIG_SYS_BL_START_FLASH      0x38040000      /* Address of relocated code */
 #define CONFIG_SYS_BL_START_RAM                0x03fd0000      /* Address of relocated code */
-#define CONFIG_SYS_MONITOR_BASE                TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE                CONFIG_SYS_TEXT_BASE
 #define CONFIG_SYS_MONITOR_LEN         (256 * 1024)    /* Reserve 256 kB for Mon       */
 #define CONFIG_SYS_FLASH_BASE          0x38000000      /* Boot Flash */
 #define CONFIG_SYS_FLASH_BASE_1                0x10000000      /* StrataFlash 1 */
@@ -233,14 +230,6 @@
 #define CONFIG_NET_MULTI
 #define CONFIG_RTL8139
 
-/*-----------------------------------------------------------------------
- * Hardware watchdog configuration
- */
-#define CONFIG_SYS_WATCHDOG_PIO_BIT            0x8000
-#define CONFIG_SYS_WATCHDIG_PIO_DATA           SC520_PIODATA15_0
-#define CONFIG_SYS_WATCHDIG_PIO_CLR            SC520_PIOCLR15_0
-#define CONFIG_SYS_WATCHDIG_PIO_SET            SC520_PIOSET15_0
-
 /*-----------------------------------------------------------------------
  * FPGA configuration
  */