FSL DDR: Convert STXSSA to new DDR code.

[u-boot] / include / configs / ep82xxm.h

diff --git a/include/configs/ep82xxm.h b/include/configs/ep82xxm.h
index 5fa70164e942dab684c3aa7c0fbfa71998f382bc..ac68c869a732efc51259d0ab9fd77c483adf20bb 100644 (file)
--- a/include/configs/ep82xxm.h
+++ b/include/configs/ep82xxm.h
@@ -31,8 +31,6 @@
 #define CONFIG_EP82XXM /* Embedded Planet EP82xxM H 1.0 board */
                        /* 256MB SDRAM / 64MB FLASH */
 
-#undef DEBUG
-
 #define CONFIG_BOARD_EARLY_INIT_F 1    /* Call board_early_init_f */
 
 /* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */
@@ -60,8 +58,8 @@
  * SCC, 1-3 for FCC)
  *
  * If CONFIG_ETHER_NONE is defined, then either the ethernet routines
- * must be defined elsewhere (as for the console), or CFG_CMD_NET must
- * be removed from CONFIG_COMMANDS to remove support for networking.
+ * must be defined elsewhere (as for the console), or CONFIG_CMD_NET
+ * must be unset.
  */
 #undef CONFIG_ETHER_ON_SCC             /* Ethernet is not on SCC */
 #define CONFIG_ETHER_ON_FCC            /* Ethernet is on FCC     */
@@ -109,6 +107,15 @@
 #define CFG_VXWORKS_MAC_PTR 0x4300 /* Pass Ethernet MAC to VxWorks */
 
 
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
 /*
  * Command line configuration.
  */
@@ -195,7 +202,7 @@
  *----------------------------------------------------------------------*/
 #define CFG_FLASH_BASE         0xFC000000
 #define CFG_FLASH_CFI
-#define CFG_FLASH_CFI_DRIVER
+#define CONFIG_FLASH_CFI_DRIVER
 #define CFG_MAX_FLASH_BANKS    1       /* max num of flash banks       */
 #define CFG_MAX_FLASH_SECT     512     /* max num of sects on one chip */
 #define CFG_FLASH_EMPTY_INFO           /* print 'E' for empty sector in flinfo */
@@ -222,7 +229,7 @@
 #endif /* CFG_ENV_IS_IN_EEPROM */
 
 /* RTC Configuration */
-#define CONFIG_RTC_M41T11      1       /* uses a M41T81 */
+#define CONFIG_RTC_M41T11      1       /* uses a M41T81 */
 #define CFG_I2C_RTC_ADDR       0x68
 #define CONFIG_M41T11_BASE_YEAR        1900
 
@@ -318,13 +325,13 @@
 #define CFG_JFFS2_LAST_SECTOR   62
 #define CFG_JFFS2_SORT_FRAGMENTS
 #define CFG_JFFS_CUSTOM_PART
-#endif /* CFG_CMD_JFFS2 */
+#endif
 
 #if defined(CONFIG_CMD_I2C)
 #define CONFIG_HARD_I2C                1       /* To enable I2C support        */
 #define CFG_I2C_SPEED          100000  /* I2C speed                    */
 #define CFG_I2C_SLAVE          0x7F    /* I2C slave address            */
-#endif /* CFG_CMD_I2C */
+#endif
 
 #define CFG_MONITOR_BASE       TEXT_BASE
 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
@@ -346,13 +353,13 @@
 /* Hard reset configuration word */
 #define CFG_HRCW_MASTER                0 /*0x1C800641*/  /* Not used - provided by CPLD */
 /* No slaves */
-#define CFG_HRCW_SLAVE1        0
-#define CFG_HRCW_SLAVE2        0
-#define CFG_HRCW_SLAVE3        0
-#define CFG_HRCW_SLAVE4        0
-#define CFG_HRCW_SLAVE5        0
-#define CFG_HRCW_SLAVE6        0
-#define CFG_HRCW_SLAVE7        0
+#define CFG_HRCW_SLAVE1                0
+#define CFG_HRCW_SLAVE2                0
+#define CFG_HRCW_SLAVE3                0
+#define CFG_HRCW_SLAVE4                0
+#define CFG_HRCW_SLAVE5                0
+#define CFG_HRCW_SLAVE6                0
+#define CFG_HRCW_SLAVE7                0
 
 #define BOOTFLAG_COLD          0x01    /* Normal Power-On: Boot from FLASH */
 #define BOOTFLAG_WARM          0x02    /* Software reboot                  */