FSL DDR: Convert STXSSA to new DDR code.

[u-boot] / include / configs / hermes.h

diff --git a/include/configs/hermes.h b/include/configs/hermes.h
index 91117bab726242f00eeb9a5253e86dca829bc46b..48b23bdcd64c08d75e659c329ce047cf2a97cae0 100644 (file)
--- a/include/configs/hermes.h
+++ b/include/configs/hermes.h
@@ -54,9 +54,9 @@
 
 #undef CONFIG_BOOTARGS
 #define CONFIG_BOOTCOMMAND                                                     \
-       "bootp; "                                                               \
-       "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "     \
-       "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "   \
+       "bootp; "                                                               \
+       "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "     \
+       "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "   \
        "bootm"
 
 #define CONFIG_LOADS_ECHO      1       /* echo on for serial download  */
@@ -64,23 +64,28 @@
 
 #undef CONFIG_WATCHDOG                 /* watchdog disabled            */
 
-#define CONFIG_COMMANDS                CONFIG_CMD_DFL
 
-#define CONFIG_BOOTP_MASK      CONFIG_BOOTP_DEFAULT
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
 
-/*----------------------------------------------------------------------*/
 
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
 
-/*----------------------------------------------------------------------*/
 
 /*
  * Miscellaneous configurable options
  */
 #define        CFG_LONGHELP                    /* undef to save memory         */
 #define        CFG_PROMPT      "=> "           /* Monitor Command Prompt       */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
 #define        CFG_CBSIZE      1024            /* Console I/O Buffer Size      */
 #else
 #define        CFG_CBSIZE      256             /* Console I/O Buffer Size      */
@@ -100,7 +105,7 @@
 
 #define CFG_BAUDRATE_TABLE     { 9600, 19200, 38400, 57600, 115200 }
 
-#define        CFG_ALLOC_DPRAM         1       /* use allocation routines      */
+#define        CFG_ALLOC_DPRAM         1       /* use allocation routines      */
 /*
  * Low Level Configuration Settings
  * (address mappings, register initial values, etc.)
@@ -157,7 +162,7 @@
  * Cache Configuration
  */
 #define CFG_CACHELINE_SIZE     16      /* For all MPC8xx CPUs                  */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
 #define CFG_CACHELINE_SHIFT    4       /* log base 2 of the above value        */
 #endif
 
@@ -222,7 +227,7 @@
 /* +0x0282 => 0x03800000 */
 #define CFG_SCCR       (SCCR_COM00     |   SCCR_TBS      |     \
                         SCCR_RTDIV     |   SCCR_RTSEL    |     \
-                        /*SCCR_CRQEN|*/  /*SCCR_PRQEN|*/       \
+                        /*SCCR_CRQEN|*/  /*SCCR_PRQEN|*/       \
                         SCCR_EBDF00    |   SCCR_DFSYNC00 |     \
                         SCCR_DFBRG00   |   SCCR_DFNL000  |     \
                         SCCR_DFNH000)