stm32mp1: add eMMC support for ED1

[u-boot] / include / configs / hsdk.h

diff --git a/include/configs/hsdk.h b/include/configs/hsdk.h
index 3b306c70ad182f5553e77c016d1e03440cc78660..ac86f3114255055c847a7079beb59f1793968e01 100644 (file)
--- a/include/configs/hsdk.h
+++ b/include/configs/hsdk.h
@@ -12,6 +12,7 @@
 /*
  *  CPU configuration
  */
+#define NR_CPUS                                4
 #define ARC_PERIPHERAL_BASE            0xF0000000
 #define ARC_DWMMC_BASE                 (ARC_PERIPHERAL_BASE + 0xA000)
 #define ARC_DWGMAC_BASE                        (ARC_PERIPHERAL_BASE + 0x18000)
@@ -29,7 +30,7 @@
        (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
 
 #define CONFIG_SYS_MALLOC_LEN          SZ_2M
-#define CONFIG_SYS_BOOTM_LEN           SZ_32M
+#define CONFIG_SYS_BOOTM_LEN           SZ_128M
 #define CONFIG_SYS_LOAD_ADDR           0x82000000
 
 /*
@@ -61,6 +62,50 @@
  */
 #define CONFIG_ENV_SIZE                        SZ_16K
 
+#define CONFIG_EXTRA_ENV_SETTINGS \
+       "core_dccm_0=0x10\0" \
+       "core_dccm_1=0x6\0" \
+       "core_dccm_2=0x10\0" \
+       "core_dccm_3=0x6\0" \
+       "core_iccm_0=0x10\0" \
+       "core_iccm_1=0x6\0" \
+       "core_iccm_2=0x10\0" \
+       "core_iccm_3=0x6\0" \
+       "core_mask=0xF\0" \
+       "dcache_ena=0x1\0" \
+       "icache_ena=0x1\0" \
+       "non_volatile_limit=0xE\0" \
+       "hsdk_hs34=setenv core_mask 0x2; setenv icache_ena 0x0; \
+setenv dcache_ena 0x0; setenv core_iccm_1 0x7; \
+setenv core_dccm_1 0x8; setenv non_volatile_limit 0x0;\0" \
+       "hsdk_hs36=setenv core_mask 0x1; setenv icache_ena 0x1; \
+setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \
+setenv core_dccm_0 0x10; setenv non_volatile_limit 0xE;\0" \
+       "hsdk_hs36_ccm=setenv core_mask 0x2; setenv icache_ena 0x1; \
+setenv dcache_ena 0x1; setenv core_iccm_1 0x7; \
+setenv core_dccm_1 0x8; setenv non_volatile_limit 0xE;\0" \
+       "hsdk_hs38=setenv core_mask 0x1; setenv icache_ena 0x1; \
+setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \
+setenv core_dccm_0 0x10; setenv non_volatile_limit 0xE;\0" \
+       "hsdk_hs38_ccm=setenv core_mask 0x2; setenv icache_ena 0x1; \
+setenv dcache_ena 0x1; setenv core_iccm_1 0x7; \
+setenv core_dccm_1 0x8; setenv non_volatile_limit 0xE;\0" \
+       "hsdk_hs38x2=setenv core_mask 0x3; setenv icache_ena 0x1; \
+setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \
+setenv core_dccm_0 0x10; setenv non_volatile_limit 0xE; \
+setenv core_iccm_1 0x6; setenv core_dccm_1 0x6;\0" \
+       "hsdk_hs38x3=setenv core_mask 0x7; setenv icache_ena 0x1; \
+setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \
+setenv core_dccm_0 0x10; setenv non_volatile_limit 0xE; \
+setenv core_iccm_1 0x6; setenv core_dccm_1 0x6; \
+setenv core_iccm_2 0x10; setenv core_dccm_2 0x10;\0" \
+       "hsdk_hs38x4=setenv core_mask 0xF; setenv icache_ena 0x1; \
+setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \
+setenv core_dccm_0 0x10; setenv non_volatile_limit 0xE; \
+setenv core_iccm_1 0x6; setenv core_dccm_1 0x6; \
+setenv core_iccm_2 0x10; setenv core_dccm_2 0x10; \
+setenv core_iccm_3 0x6; setenv core_dccm_3 0x6;\0"
+
 /*
  * Environment configuration
  */
@@ -68,17 +113,17 @@
 #define CONFIG_LOADADDR                        CONFIG_SYS_LOAD_ADDR
 
 /*
- * Console configuration
+ * Misc utility configuration
  */
-#define CONFIG_AUTO_COMPLETE
-#define CONFIG_CMDLINE_EDITING
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_SYS_MAXARGS             16
-#define CONFIG_SYS_BARGSIZE            CONFIG_SYS_CBSIZE
+#define CONFIG_BOUNCE_BUFFER
+
+/* Cli configuration */
+#define CONFIG_SYS_CBSIZE              SZ_2K
 
 /*
- * Misc utility configuration
+ * Callback configuration
  */
-#define CONFIG_BOUNCE_BUFFER
+#define CONFIG_BOARD_EARLY_INIT_R
+#define CONFIG_BOARD_LATE_INIT
 
 #endif /* _CONFIG_HSDK_H_ */