]> git.sur5r.net Git - u-boot/blobdiff - include/configs/igep0030.h
ARM: OMAP3: Remove unused define SDRC_R_C_B
[u-boot] / include / configs / igep0030.h
index d6fbec7b1f18abbdee05570985e59357b39131c9..36346187f8898048bb02e1dd1325e54d31b01ebf 100644 (file)
 /*
  * High Level Configuration Options
  */
-#define CONFIG_ARMV7           1       /* This is an ARM V7 CPU core */
 #define CONFIG_OMAP            1       /* in a TI OMAP core */
 #define CONFIG_OMAP34XX                1       /* which is a 34XX */
-#define CONFIG_OMAP3430                1       /* which is in a 3430 */
 #define CONFIG_OMAP3_IGEP0030  1       /* working with IGEP0030 */
 
 #define CONFIG_SDRC    /* The chip has SDRC controller */
@@ -53,6 +51,8 @@
 #define CONFIG_INITRD_TAG              1
 #define CONFIG_REVISION_TAG            1
 
+#define CONFIG_OF_LIBFDT               1
+
 /*
  * NS16550 Configuration
  */
@@ -73,8 +73,9 @@
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_BAUDRATE                        115200
 #define CONFIG_SYS_BAUDRATE_TABLE      {4800, 9600, 19200, 38400, 57600, 115200}
+#define CONFIG_GENERIC_MMC             1
 #define CONFIG_MMC                     1
-#define CONFIG_OMAP3_MMC               1
+#define CONFIG_OMAP_HSMMC              1
 #define CONFIG_DOS_PARTITION           1
 
 /* DDR  */
 #define CONFIG_MTD_DEVICE
 
 #undef CONFIG_CMD_NET          /* bootp, tftpboot, rarpboot    */
+#undef CONFIG_CMD_NFS          /* nfs                          */
 #undef CONFIG_CMD_FLASH                /* flinfo, erase, protect       */
 #undef CONFIG_CMD_IMLS         /* List all found images        */
 
  */
 #define CONFIG_TWL4030_POWER           1
 
-/* Environment information */
-#define CONFIG_BOOTCOMMAND \
-       "mmc init 0 ; fatload mmc 0 0x80000000 setup.ini ; source \0"
-
 #define CONFIG_BOOTDELAY               3
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
-       "usbtty=cdc_acm\0"
+       "usbtty=cdc_acm\0" \
+       "loadaddr=0x82000000\0" \
+       "usbtty=cdc_acm\0" \
+       "console=ttyS2,115200n8\0" \
+       "mpurate=500\0" \
+       "vram=12M\0" \
+       "dvimode=1024x768MR-16@60\0" \
+       "defaultdisplay=dvi\0" \
+       "mmcdev=0\0" \
+       "mmcroot=/dev/mmcblk0p2 rw\0" \
+       "mmcrootfstype=ext3 rootwait\0" \
+       "nandroot=/dev/mtdblock4 rw\0" \
+       "nandrootfstype=jffs2\0" \
+       "mmcargs=setenv bootargs console=${console} " \
+               "mpurate=${mpurate} " \
+               "vram=${vram} " \
+               "omapfb.mode=dvi:${dvimode} " \
+               "omapfb.debug=y " \
+               "omapdss.def_disp=${defaultdisplay} " \
+               "root=${mmcroot} " \
+               "rootfstype=${mmcrootfstype}\0" \
+       "nandargs=setenv bootargs console=${console} " \
+               "mpurate=${mpurate} " \
+               "vram=${vram} " \
+               "omapfb.mode=dvi:${dvimode} " \
+               "omapfb.debug=y " \
+               "omapdss.def_disp=${defaultdisplay} " \
+               "root=${nandroot} " \
+               "rootfstype=${nandrootfstype}\0" \
+       "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
+       "bootscript=echo Running bootscript from mmc ...; " \
+               "source ${loadaddr}\0" \
+       "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
+       "mmcboot=echo Booting from mmc ...; " \
+               "run mmcargs; " \
+               "bootm ${loadaddr}\0" \
+       "nandboot=echo Booting from onenand ...; " \
+               "run nandargs; " \
+               "onenand read ${loadaddr} 280000 400000; " \
+               "bootm ${loadaddr}\0" \
+
+#define CONFIG_BOOTCOMMAND \
+       "if mmc rescan ${mmcdev}; then " \
+               "if run loadbootscript; then " \
+                       "run bootscript; " \
+               "else " \
+                       "if run loaduimage; then " \
+                               "run mmcboot; " \
+                       "else run nandboot; " \
+                       "fi; " \
+               "fi; " \
+       "else run nandboot; fi"
 
 #define CONFIG_AUTO_COMPLETE           1
 
 #define PHYS_SDRAM_1_SIZE      (32 << 20)      /* at least 32 meg */
 #define PHYS_SDRAM_2           OMAP34XX_SDRC_CS1
 
-/* SDRAM Bank Allocation method */
-#define SDRC_R_B_C             1
-
 /*
  * FLASH and environment organization
  */
 #define CONFIG_SYS_MALLOC_LEN          (CONFIG_ENV_SIZE + (128 << 10))
 
 #define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_SP_ADDR                (LOW_LEVEL_SRAM_STACK - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_ADDR       0x4020f800
+#define CONFIG_SYS_INIT_RAM_SIZE       0x800
+#define CONFIG_SYS_INIT_SP_ADDR                (CONFIG_SYS_INIT_RAM_ADDR + \
+                                        CONFIG_SYS_INIT_RAM_SIZE - \
+                                        GENERATED_GBL_DATA_SIZE)
 
 #endif /* __CONFIG_H */