microblaze: Enable TFTP put command

[u-boot] / include / configs / igep0030.h

diff --git a/include/configs/igep0030.h b/include/configs/igep0030.h
index 713b1b9e69f32517139c09d61f246974322cfabf..bf39ba56d792fb40e51e7de33268b6831f1e45c4 100644 (file)
--- a/include/configs/igep0030.h
+++ b/include/configs/igep0030.h
@@ -25,10 +25,8 @@
 /*
  * High Level Configuration Options
  */
-#define CONFIG_ARMV7           1       /* This is an ARM V7 CPU core */
 #define CONFIG_OMAP            1       /* in a TI OMAP core */
 #define CONFIG_OMAP34XX                1       /* which is a 34XX */
-#define CONFIG_OMAP3430                1       /* which is in a 3430 */
 #define CONFIG_OMAP3_IGEP0030  1       /* working with IGEP0030 */
 
 #define CONFIG_SDRC    /* The chip has SDRC controller */
@@ -53,6 +51,8 @@
 #define CONFIG_INITRD_TAG              1
 #define CONFIG_REVISION_TAG            1
 
+#define CONFIG_OF_LIBFDT               1
+
 /*
  * NS16550 Configuration
  */
@@ -78,9 +78,6 @@
 #define CONFIG_OMAP_HSMMC              1
 #define CONFIG_DOS_PARTITION           1
 
-/* DDR  */
-#define CONFIG_OMAP3_NUMONYX_DDR       1
-
 /* USB */
 #define CONFIG_MUSB_UDC                        1
 #define CONFIG_USB_OMAP3               1
@@ -235,9 +232,6 @@
 #define PHYS_SDRAM_1_SIZE      (32 << 20)      /* at least 32 meg */
 #define PHYS_SDRAM_2           OMAP34XX_SDRC_CS1
 
-/* SDRAM Bank Allocation method */
-#define SDRC_R_B_C             1
-
 /*
  * FLASH and environment organization
  */