Add support for SRAM and 2 x Quad UARTs on INKA4x0 board

[u-boot] / include / configs / inka4x0.h

diff --git a/include/configs/inka4x0.h b/include/configs/inka4x0.h
index eb1256a5d87e9bfb322686c7cb77a24febd93bd3..15b124a2ab1e767d335f24cda62597452ea47e96 100644 (file)
--- a/include/configs/inka4x0.h
+++ b/include/configs/inka4x0.h
@@ -29,25 +29,27 @@
  * (easy to change)
  */
 
-#define CONFIG_MPC5xxx         1       /* This is an MPC5xxx CPU */
-#define CONFIG_MPC5200         1       /* (more precisely an MPC5200 CPU) */
-#define CONFIG_INKA4X0         1       /* INKA4x0 board */
+#define CONFIG_MPC5xxx         1       /* This is an MPC5xxx CPU               */
+#define CONFIG_MPC5200         1       /* (more precisely an MPC5200 CPU)      */
+#define CONFIG_INKA4X0         1       /* INKA4x0 board                        */
 
-#define CFG_MPC5XXX_CLKIN      33000000 /* ... running at 33.000000MHz */
+#define CFG_MPC5XXX_CLKIN      33000000 /* ... running at 33.000000MHz         */
 
-#define BOOTFLAG_COLD          0x01    /* Normal Power-On: Boot from FLASH  */
-#define BOOTFLAG_WARM          0x02    /* Software reboot           */
+#define BOOTFLAG_COLD          0x01    /* Normal Power-On: Boot from FLASH     */
+#define BOOTFLAG_WARM          0x02    /* Software reboot                      */
 
-#define CFG_CACHELINE_SIZE     32      /* For MPC5xxx CPUs */
+#define CONFIG_MISC_INIT_F     1       /* Use misc_init_f()                    */
+
+#define CFG_CACHELINE_SIZE     32      /* For MPC5xxx CPUs                     */
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#  define CFG_CACHELINE_SHIFT  5       /* log base 2 of the above value */
+#  define CFG_CACHELINE_SHIFT  5       /* log base 2 of the above value        */
 #endif
 
 /*
  * Serial console configuration
  */
-#define CONFIG_PSC_CONSOLE     1       /* console is on PSC1 */
-#define CONFIG_BAUDRATE                115200  /* ... at 115200 bps */
+#define CONFIG_PSC_CONSOLE     1       /* console is on PSC1   */
+#define CONFIG_BAUDRATE                115200  /* ... at 115200 bps    */
 #define CFG_BAUDRATE_TABLE     { 9600, 19200, 38400, 57600, 115200, 230400 }
 
 /*
@@ -257,6 +259,16 @@
 #define CFG_CS0_START          CFG_FLASH_BASE
 #define CFG_CS0_SIZE           CFG_FLASH_SIZE
 
+/* 32Mbit SRAM @0x30000000 */
+#define CFG_CS1_START          0x30000000
+#define CFG_CS1_SIZE           0x00400000
+#define CFG_CS1_CFG            0x31800 /* for pci_clk = 33 MHz */
+
+/* 2 quad UART @0x80000000 (MBAR is relocated to 0xF0000000) */
+#define CFG_CS2_START          0x80000000
+#define CFG_CS2_SIZE           0x0001000
+#define CFG_CS2_CFG            0x21800  /* for pci_clk = 33 MHz */
+
 #define CFG_CS_BURST           0x00000000
 #define CFG_CS_DEADCYCLE       0x33333333
 
@@ -265,7 +277,8 @@
  *-----------------------------------------------------------------------
  */
 #define CONFIG_USB_OHCI
-#define CONFIG_USB_CLOCK        0x00015555
-#define CONFIG_USB_CONFIG       0x00001000
+#define CONFIG_USB_CLOCK       0x00015555
+#define CONFIG_USB_CONFIG      0x00001000
+#define CONFIG_USB_STORAGE
 
 #endif /* __CONFIG_H */