#ifndef __CONFIG_H
#define __CONFIG_H
-#define DEBUG 1
-
-/*
- * If we are developing, we might want to start U-Boot from ram
- * so we MUST NOT initialize critical regs like mem-timing ...
- */
-#define CONFIG_INIT_CRITICAL /* undef for developing */
-
/*
* High Level Configuration Options
* (easy to change)
#define CONFIG_ENV_OVERWRITE
#define CONFIG_BAUDRATE 19200
+#define CONFIG_MISC_INIT_R 1 /* we have a misc_init_r() function */
-#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_I2C | CFG_CMD_EEPROM) & ~CFG_CMD_NET)
-
+#define CONFIG_COMMANDS (CFG_CMD_BDI|CFG_CMD_LOADB|CFG_CMD_IMI|CFG_CMD_FLASH|CFG_CMD_MEMORY|CFG_CMD_NET|CFG_CMD_ENV|CFG_CMD_RUN|CFG_CMD_ASKENV|CFG_CMD_ECHO|CFG_CMD_I2C|CFG_CMD_DHCP|CFG_CMD_CACHE)
+/* CONFIG_CMD_DFL|CFG_CMD_I2C|CFG_CMD_EEPROM|CFG_CMD_NET|CFG_CMD_JFFS2|CFG_CMD_DHCP) */
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
#define CONFIG_CMDLINE_TAG 1
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 19200 /* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
-#endif
-
/*
* Miscellaneous configurable options
*/
/*
- * Size of malloc() pool; this lives below the uppermost 128 KiB which are
- * used for the RAM copy of the uboot code
+ * Size of malloc() pool
*/
-/* #define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) */
-#define CFG_MALLOC_LEN (128*1024)
+#define CFG_MALLOC_LEN (256*1024)
+#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "uboot> " /* Monitor Command Prompt */
-#define CFG_CBSIZE 128 /* Console I/O Buffer Size */
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
-#define CFG_LOAD_ADDR 0xa7fe0000 /* default load address */
- /* RS: where is this documented? */
- /* RS: is this where U-Boot is */
- /* RS: relocated to in RAM? */
+#define CFG_LOAD_ADDR 0xa3000000 /* load kernel to this address */
#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */
/* RS: the oscillator is actually 3680130?? */
#define CFG_MONITOR_LEN 0x20000 /* 128 KiB */
- /* valid baudrates */
+ /* valid baudrates */
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
/*
* I2C bus
*/
-#define CONFIG_HARD_I2C 1
-#define CFG_I2C_SPEED 50000
-#define CFG_I2C_SLAVE 0xfe
+#define CONFIG_HARD_I2C 1
+#define CFG_I2C_SPEED 50000
+#define CFG_I2C_SLAVE 0xfe
#define CFG_ENV_IS_IN_EEPROM 1
#define CFG_ENV_SIZE 1024 /* 1 KiB */
#define CFG_I2C_EEPROM_ADDR 0x50 /* A0 = 0 (hardwired) */
#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* 5 bits = 32 octets */
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* between stop and start */
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 15 /* between stop and start */
#define CFG_I2C_EEPROM_ADDR_LEN 2 /* length of address */
#define CFG_EEPROM_SIZE 4096 /* size in bytes */
+#define CFG_I2C_INIT_BOARD 1 /* board has it's own init */
+
+/*
+ * SMSC91C111 Network Card
+ */
+#define CONFIG_DRIVER_SMC91111 1
+#define CONFIG_SMC91111_BASE 0x14000000 /* chip select 5 */
+#undef CONFIG_SMC_USE_32_BIT /* 16 bit bus access */
+#undef CONFIG_SMC_91111_EXT_PHY /* we use internal phy */
+#define CONFIG_SMC_AUTONEG_TIMEOUT 10 /* timeout 10 seconds */
+#undef CONFIG_SHOW_ACTIVITY
+#define CONFIG_NET_RETRY_COUNT 10 /* # of retries */
/*
* Stack sizes
#define CFG_FLASH_BASE PHYS_FLASH_1
/*
- * GPIO settings;
+ * JFFS2 partitions
+ *
*/
+/* development flash */
+#define CONFIG_MTD_INNOKOM_16MB 1
+#undef CONFIG_MTD_INNOKOM_64MB
+
+/* production flash */
+/*
+#define CONFIG_MTD_INNOKOM_64MB 1
+#undef CONFIG_MTD_INNOKOM_16MB
+*/
+
+/* No command line, one static partition, whole device */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV "nor0"
+#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
+#define CONFIG_JFFS2_PART_OFFSET 0x00000000
-/* GP15 == nCS1 is 1
+/* mtdparts command line support */
+/* Note: fake mtd_id used, no linux mtd map file */
+/*
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT "nor0=innokom-0"
+*/
+
+/* development flash */
+/*
+#define MTDPARTS_DEFAULT "mtdparts=innokom-0:256k(uboot),768k(kernel),8m(user),7m(data)"
+*/
+
+/* production flash */
+/*
+#define MTDPARTS_DEFAULT "mtdparts=innokom-0:256k(uboot),768k(kernel),16256k(user1),16256k(user2),32m(data)"
+*/
+
+/*
+ * GPIO settings
+ *
+ * GP15 == nCS1 is 1
* GP24 == SFRM is 1
* GP25 == TXD is 1
* GP33 == nCS5 is 1
#define CFG_GAFR2_L_VAL 0xA0000000
#define CFG_GAFR2_U_VAL 0x00000002
+
/* FIXME: set GPIO_RER/FER */
/* RDH = 1
/*
* Memory settings
- */
-
-/* This is the configuration for nCS0/1 -> flash banks
+ *
+ * This is the configuration for nCS0/1 -> flash banks
* configuration for nCS1:
* [31] 0 - Slower Device
* [30:28] 010 - CS deselect to CS time: 2*(2*MemClk) = 40 ns
* [03] 1 - 16 Bit bus width
* [02:00] 100 - variable latency I/O
*/
-#define CFG_MSC1_VAL 0x132C593C /* TDM switch, DSP */
+#define CFG_MSC1_VAL 0x123C593C /* TDM switch, DSP */
/* This is the configuration for nCS4/5 -> ExtBus, LAN Controller
*
* [03] 1 - 16 Bit bus width
* [02:00] 100 - variable latency I/O
*/
-#define CFG_MSC2_VAL 0x132C6CDC /* extra bus, LAN controller */
+#define CFG_MSC2_VAL 0x123C6CDC /* extra bus, LAN controller */
/* MDCNFG: SDRAM Configuration Register
*
* [12] 1 - SA1111 compatiblity mode
* [11] 1 - latch return data with return clock
* [10] 0 - no alternate addressing for pair 0/1
- * [09:08] 01 - tRP=2*MemClk; CL=2; tRCD=2*MemClk; tRAS=5*MemClk; tRC=8*MemClk
+ * [09:08] 01 - tRP=2*MemClk CL=2 tRCD=2*MemClk tRAS=5*MemClk tRC=8*MemClk
* [7] 1 - 4 internal banks in lower partition pair
* [06:05] 10 - 13 row address bits for partition 0/1
* [04:03] 01 - 9 column address bits for partition 0/1
* [02] 0 - SDRAM partition 0/1 width is 32 bit
* [01] 0 - disable SDRAM partition 1
* [00] 1 - enable SDRAM partition 0
- *
- * use the configuration above but disable partition 0
*/
+/* use the configuration above but disable partition 0 */
#define CFG_MDCNFG_VAL 0x000019c8
/* MDREFR: SDRAM Refresh Control Register
* [32:26] 0 - reserved
* [25] 0 - K2FREE: not free running
* [24] 0 - K1FREE: not free running
- * [23] 0 - K0FREE: not free running
+ * [23] 1 - K0FREE: not free running
* [22] 0 - SLFRSH: self refresh disabled
* [21] 0 - reserved
* [20] 0 - APD: no auto power down
* [16] 1 - K1RUN: enable SDCLK1
* [15] 1 - E1PIN: SDRAM clock enable
* [14] 1 - K0DB2: SDCLK0 is MemClk
- * [13] 1 - K0RUN: disable SDCLK0
+ * [13] 0 - K0RUN: disable SDCLK0
* [12] 1 - E0PIN: disable SDCKE0
* [11:00] 000000011000 - (64ms/8192)*MemClkFreq/32 = 24
*/
-#define CFG_MDREFR_VAL 0x0001F018
+#define CFG_MDREFR_VAL 0x0081D018
/* MDMRS: Mode Register Set Configuration Register
*
#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */
#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */
-#if 0
-#define CFG_ENV_IS_IN_FLASH 1
-#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x1C000)
- /* Addr of Environment Sector */
-#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
-#endif
-
#endif /* __CONFIG_H */
projects / u-boot / blobdiff