Merge branch 'master' of git://git.denx.de/u-boot-video

[u-boot] / include / configs / km / km83xx-common.h

diff --git a/include/configs/km/km83xx-common.h b/include/configs/km/km83xx-common.h
index 2014e3770a169c9a6b69caa8c3b56a9d22286a99..877d8418c0a36049c696e96c139c0d41bd346072 100644 (file)
--- a/include/configs/km/km83xx-common.h
+++ b/include/configs/km/km83xx-common.h
@@ -15,13 +15,18 @@
 #include "keymile-common.h"
 #include "km-powerpc.h"
 
-#define MTDIDS_DEFAULT         "nor0=boot"
-#define MTDPARTS_DEFAULT       "mtdparts="                     \
+#ifndef MTDIDS_DEFAULT
+# define MTDIDS_DEFAULT        "nor0=boot"
+#endif /* MTDIDS_DEFAULT */
+
+#ifndef MTDPARTS_DEFAULT
+# define MTDPARTS_DEFAULT      "mtdparts="                     \
        "boot:"                                                 \
                "768k(u-boot),"                                 \
                "128k(env),"                                    \
                "128k(envred),"                                 \
-               "-(" CONFIG_KM_UBI_PARTITION_NAME ")"
+               "-(" CONFIG_KM_UBI_PARTITION_NAME_BOOT ");"
+#endif /* MTDPARTS_DEFAULT */
 
 #define CONFIG_MISC_INIT_R
 /*
@@ -49,6 +54,8 @@
  */
 #define CONFIG_SYS_DDR_BASE            0x00000000 /* DDR is system memory */
 #define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
+
 #define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_DDR_BASE
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL  (DDR_SDRAM_CLK_CNTL_SS_EN | \
                                        DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
@@ -103,16 +110,17 @@
 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 
 #define CONFIG_SYS_LBLAWBAR0_PRELIM    CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_LBLAWAR0_PRELIM     0x8000001b /* 256MB window size */
+#define CONFIG_SYS_LBLAWAR0_PRELIM     (LBLAWAR_EN | LBLAWAR_256MB)
 
 #define CONFIG_SYS_BR0_PRELIM  (CONFIG_SYS_FLASH_BASE | \
-                               (2 << BR_PS_SHIFT) | /* 16 bit port size */ \
+                               BR_PS_16 | /* 16 bit port size */ \
+                               BR_MS_GPCM | /* MSEL = GPCM */ \
                                BR_V)
 
 #define CONFIG_SYS_OR0_PRELIM  (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \
                                OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
                                OR_GPCM_SCY_5 | \
-                               OR_GPCM_TRLX | OR_GPCM_EAD)
+                               OR_GPCM_TRLX_SET | OR_GPCM_EAD)
 
 #define CONFIG_SYS_MAX_FLASH_BANKS     1   /* max num of flash banks   */
 #define CONFIG_SYS_MAX_FLASH_SECT      512 /* max num of sects on one chip */
@@ -123,15 +131,16 @@
  */
 /* Window base at flash base */
 #define CONFIG_SYS_LBLAWBAR1_PRELIM    CONFIG_SYS_KMBEC_FPGA_BASE
-#define CONFIG_SYS_LBLAWAR1_PRELIM     0x8000001A /* 128MB window size */
+#define CONFIG_SYS_LBLAWAR1_PRELIM     (LBLAWAR_EN | LBLAWAR_128MB)
 
 #define CONFIG_SYS_BR1_PRELIM  (CONFIG_SYS_KMBEC_FPGA_BASE | \
-                               (1 << BR_PS_SHIFT) | /* 8 bit port size */ \
+                               BR_PS_8 | /* 8 bit port size */ \
+                               BR_MS_GPCM | /* MSEL = GPCM */ \
                                BR_V)
 #define CONFIG_SYS_OR1_PRELIM  (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) | \
                                OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
                                OR_GPCM_SCY_2 | \
-                               OR_GPCM_TRLX | OR_GPCM_EAD)
+                               OR_GPCM_TRLX_SET | OR_GPCM_EAD)
 
 /*
  * Serial Port
@@ -239,7 +248,7 @@
 #define CONFIG_HIGH_BATS       1       /* High BATs supported */
 
 /* DDR: cache cacheable */
-#define CONFIG_SYS_IBAT0L      (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | \
+#define CONFIG_SYS_IBAT0L      (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
                                BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 #define CONFIG_SYS_IBAT0U      (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \
                                        BATU_VS | BATU_VP)
@@ -247,7 +256,7 @@
 #define CONFIG_SYS_DBAT0U      CONFIG_SYS_IBAT0U
 
 /* IMMRBAR & PCI IO: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT1L      (CONFIG_SYS_IMMR | BATL_PP_10 | \
+#define CONFIG_SYS_IBAT1L      (CONFIG_SYS_IMMR | BATL_PP_RW | \
                                BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 #define CONFIG_SYS_IBAT1U      (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS \
                                        | BATU_VP)
@@ -255,25 +264,25 @@
 #define CONFIG_SYS_DBAT1U      CONFIG_SYS_IBAT1U
 
 /* PRIO1, PIGGY:  icache cacheable, but dcache-inhibit and guarded */
-#define CONFIG_SYS_IBAT2L      (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_10 | \
+#define CONFIG_SYS_IBAT2L      (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \
                                BATL_MEMCOHERENCE)
 #define CONFIG_SYS_IBAT2U      (CONFIG_SYS_KMBEC_FPGA_BASE | BATU_BL_128M | \
                                BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT2L      (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_10 | \
+#define CONFIG_SYS_DBAT2L      (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \
                                 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 #define CONFIG_SYS_DBAT2U      CONFIG_SYS_IBAT2U
 
 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
-#define CONFIG_SYS_IBAT3L      (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
+#define CONFIG_SYS_IBAT3L      (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
                                        BATL_MEMCOHERENCE)
 #define CONFIG_SYS_IBAT3U      (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | \
                                        BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT3L      (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
+#define CONFIG_SYS_DBAT3L      (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
                                 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 #define CONFIG_SYS_DBAT3U      CONFIG_SYS_IBAT3U
 
 /* Stack in dcache: cacheable, no memory coherence */
-#define CONFIG_SYS_IBAT4L      (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
+#define CONFIG_SYS_IBAT4L      (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
 #define CONFIG_SYS_IBAT4U      (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
                                        BATU_VS | BATU_VP)
 #define CONFIG_SYS_DBAT4L      CONFIG_SYS_IBAT4L