microblaze: Enable TFTP put command

[u-boot] / include / configs / kmsupx5.h

diff --git a/include/configs/kmsupx5.h b/include/configs/kmsupx5.h
index f8cd8e023e13f1b97e85f8f3e2861c2e373c41d4..b0dd88cd78098d11221255b06ca7fcdfbcbdccaa 100644 (file)
--- a/include/configs/kmsupx5.h
+++ b/include/configs/kmsupx5.h
@@ -69,16 +69,16 @@
                                 OR_GPCM_CSNT | \
                                 OR_GPCM_ACS_DIV4 | \
                                 OR_GPCM_SCY_2 | \
-                                (OR_GPCM_TRLX & \
-                                (~OR_GPCM_EHTR)) |  /* EHTR = 0 */ \
+                                OR_GPCM_TRLX_SET | \
+                                OR_GPCM_EHTR_CLEAR | \
                                 OR_GPCM_EAD)
 
 /* LPXF:  icache cacheable, but dcache-inhibit and guarded */
-#define CONFIG_SYS_IBAT5L      (CONFIG_SYS_LPXF_BASE | BATL_PP_10 | \
+#define CONFIG_SYS_IBAT5L      (CONFIG_SYS_LPXF_BASE | BATL_PP_RW | \
                                 BATL_MEMCOHERENCE)
 #define CONFIG_SYS_IBAT5U      (CONFIG_SYS_LPXF_BASE | BATU_BL_256M | \
                                 BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT5L      (CONFIG_SYS_LPXF_BASE | BATL_PP_10 | \
+#define CONFIG_SYS_DBAT5L      (CONFIG_SYS_LPXF_BASE | BATL_PP_RW | \
                                 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 #define CONFIG_SYS_DBAT5U      CONFIG_SYS_IBAT5U