+/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2017 NXP
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __LS1088_COMMON_H
/* Link Definitions */
-#define CONFIG_SUPPORT_RAW_INITRD
-
#ifdef CONFIG_QSPI_BOOT
#define CONFIG_SYS_FSL_QSPI_BASE 0x20000000
#define CONFIG_ENV_OFFSET 0x300000 /* 3MB */
/* I2C */
#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
-#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
-#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
-#define CONFIG_SYS_I2C_MXC_I2C4 /* enable I2C bus 4 */
/* Serial Port */
-#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2)
sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */
-#define CONFIG_SYS_LONGHELP
-#ifndef SPL_NO_ENV
-#define CONFIG_CMDLINE_EDITING 1
-#endif
-#define CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_MAXARGS 64 /* max command args */
#ifdef CONFIG_SPL
#define CONFIG_SPL_BSS_START_ADDR 0x80100000
#define CONFIG_SPL_BSS_MAX_SIZE 0x00100000
-#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
#define CONFIG_SPL_MAX_SIZE 0x16000
#define CONFIG_SPL_STACK (CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0)