]> git.sur5r.net Git - u-boot/blobdiff - include/configs/ls2080aqds.h
usb: move CONFIG_USB_XHCI to Kconfig with renaming
[u-boot] / include / configs / ls2080aqds.h
index a402c06a3bdd28de1f5089240da3c832ac4b4e42..743473fec845cea1fbfd9a416f2bda49336447e6 100644 (file)
@@ -44,9 +44,7 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_LIBATA
 #define CONFIG_SCSI_AHCI
 #define CONFIG_SCSI_AHCI_PLAT
-#define CONFIG_CMD_SCSI
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_EXT2
+#define CONFIG_SCSI
 #define CONFIG_DOS_PARTITION
 #define CONFIG_BOARD_LATE_INIT
 
@@ -119,7 +117,6 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_NAND_MAX_ECCPOS     256
 #define CONFIG_SYS_NAND_MAX_OOBFREE    2
 
-
 #define CONFIG_SYS_NAND_CSPR_EXT       (0x0)
 #define CONFIG_SYS_NAND_CSPR   (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
                                | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
@@ -283,7 +280,6 @@ unsigned long get_board_ddr_clk(void);
 
 /* SPI */
 #ifdef CONFIG_FSL_DSPI
-#define CONFIG_CMD_SF
 #define CONFIG_SPI_FLASH
 #endif
 
@@ -326,11 +322,9 @@ unsigned long get_board_ddr_clk(void);
 /*  MMC  */
 #define CONFIG_MMC
 #ifdef CONFIG_MMC
-#define CONFIG_CMD_MMC
 #define CONFIG_FSL_ESDHC
 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
 #define CONFIG_GENERIC_MMC
-#define CONFIG_CMD_FAT
 #define CONFIG_DOS_PARTITION
 #endif
 
@@ -346,13 +340,14 @@ unsigned long get_board_ddr_clk(void);
        "initrd_high=0xffffffffffffffff\0"      \
        "kernel_start=0x581100000\0"            \
        "kernel_load=0xa0000000\0"              \
-       "kernel_size=0x2800000\0"
+       "kernel_size=0x2800000\0"               \
+       "mcinitcmd=fsl_mc start mc 0x580300000" \
+       " 0x580800000 \0"
 
 #ifdef CONFIG_FSL_MC_ENET
 #define CONFIG_FSL_MEMAC
 #define        CONFIG_PHYLIB
 #define CONFIG_PHYLIB_10G
-#define        CONFIG_CMD_MII
 #define CONFIG_PHY_VITESSE
 #define CONFIG_PHY_REALTEK
 #define CONFIG_PHY_TERANETICS
@@ -379,7 +374,7 @@ unsigned long get_board_ddr_clk(void);
 #define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf
 
 #define CONFIG_MII             /* MII PHY management */
-#define CONFIG_ETHPRIME                "DPNI1"
+#define CONFIG_ETHPRIME                "DPMAC1@xgmii"
 #define CONFIG_PHY_GIGE                /* Include GbE speed/duplex detection */
 
 #endif
@@ -388,13 +383,12 @@ unsigned long get_board_ddr_clk(void);
  * USB
  */
 #define CONFIG_HAS_FSL_XHCI_USB
-#define CONFIG_USB_XHCI
 #define CONFIG_USB_XHCI_FSL
 #define CONFIG_USB_XHCI_DWC3
 #define CONFIG_USB_MAX_CONTROLLER_COUNT                2
 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS     2
-#define CONFIG_CMD_USB
 #define CONFIG_USB_STORAGE
-#define CONFIG_CMD_EXT2
+
+#include <asm/fsl_secure_boot.h>
 
 #endif /* __LS2_QDS_H */