#define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf
#define CONFIG_MII /* MII PHY management */
-#define CONFIG_ETHPRIME "DPNI1"
+#define CONFIG_ETHPRIME "DPMAC1@xgmii"
#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
#endif
* USB
*/
#define CONFIG_HAS_FSL_XHCI_USB
-#define CONFIG_USB_XHCI
#define CONFIG_USB_XHCI_FSL
#define CONFIG_USB_XHCI_DWC3
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2