#define CONFIG_GICV3
/* Link Definitions */
-#define CONFIG_SYS_TEXT_BASE 0x30000000
+#define CONFIG_SYS_TEXT_BASE 0x30001000
#ifdef CONFIG_EMU
#define CONFIG_SYS_NO_FLASH
#define CONFIG_SYS_FSL_DDR_INTLV_256B /* force 256 byte interleaving */
-/* SMP Definitions */
-#define CPU_RELEASE_ADDR CONFIG_SYS_INIT_SP_ADDR
-
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL
+#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 2
+
+/*
+ * SMP Definitinos
+ */
+#define CPU_RELEASE_ADDR secondary_boot_func
+
+#define CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
+#define CONFIG_SYS_DP_DDR_BASE 0x6000000000ULL
+/*
+ * DDR controller use 0 as the base address for binding.
+ * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
+ */
+#define CONFIG_SYS_DP_DDR_BASE_PHY 0
+#define CONFIG_DP_DDR_CTRL 2
+#define CONFIG_DP_DDR_NUM_CTRLS 1
+#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1
/* Generic Timer Definitions */
#define COUNTER_FREQUENCY 12000000 /* 12MHz */
/* Miscellaneous configurable options */
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
+#define CONFIG_ARCH_EARLY_INIT_R
/* Physical Memory Map */
/* fixme: these need to be checked against the board */
#define CONFIG_SYS_CLK_FREQ 133333333
-#define CONFIG_NR_DRAM_BANKS 2
-
-#define CONFIG_SYS_HZ 1000
+#define CONFIG_NR_DRAM_BANKS 3
#define CONFIG_HWCONFIG
#define HWCONFIG_BUFFER_SIZE 128