sunxi: Enable pre-console buffer

[u-boot] / include / configs / ls2085a_common.h

diff --git a/include/configs/ls2085a_common.h b/include/configs/ls2085a_common.h
index 2bd5a472b37f07f2c1ee6d991c8a6160d2d5c3e3..6fe032c9ff64fb6b89f107095af3b9f38ca4998b 100644 (file)
--- a/include/configs/ls2085a_common.h
+++ b/include/configs/ls2085a_common.h
@@ -15,9 +15,11 @@
 #define CONFIG_GICV3
 
 /* Link Definitions */
-#define CONFIG_SYS_TEXT_BASE           0x30000000
+#define CONFIG_SYS_TEXT_BASE           0x30001000
 
+#ifdef CONFIG_EMU
 #define CONFIG_SYS_NO_FLASH
+#endif
 
 #define CONFIG_SUPPORT_RAW_INITRD
 
@@ -45,13 +47,27 @@
 
 #define CONFIG_SYS_FSL_DDR_INTLV_256B  /* force 256 byte interleaving */
 
-/* SMP Definitions */
-#define CPU_RELEASE_ADDR               CONFIG_SYS_INIT_SP_ADDR
-
 #define CONFIG_SYS_DDR_SDRAM_BASE      0x80000000UL
 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY      0
 #define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_SDRAM_BASE
 #define CONFIG_SYS_DDR_BLOCK2_BASE     0x8080000000ULL
+#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS      2
+
+/*
+ * SMP Definitinos
+ */
+#define CPU_RELEASE_ADDR               secondary_boot_func
+
+#define CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
+#define CONFIG_SYS_DP_DDR_BASE         0x6000000000ULL
+/*
+ * DDR controller use 0 as the base address for binding.
+ * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
+ */
+#define CONFIG_SYS_DP_DDR_BASE_PHY     0
+#define CONFIG_DP_DDR_CTRL             2
+#define CONFIG_DP_DDR_NUM_CTRLS                1
+#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR      1
 
 /* Generic Timer Definitions */
 #define COUNTER_FREQUENCY              12000000        /* 12MHz */
@@ -118,6 +134,66 @@
 #define CONFIG_SYS_NOR_FTIM3   0x04000000
 #define CONFIG_SYS_IFC_CCR     0x01000000
 
+#ifndef CONFIG_SYS_NO_FLASH
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS     45 /* count down from 45/5: 9..1 */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS     1       /* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT      1024    /* sectors per device */
+#define CONFIG_SYS_FLASH_ERASE_TOUT    60000   /* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT    500     /* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_BANKS_LIST    { CONFIG_SYS_FLASH_BASE }
+#endif
+
+#define CONFIG_NAND_FSL_IFC
+#define CONFIG_SYS_NAND_MAX_ECCPOS     256
+#define CONFIG_SYS_NAND_MAX_OOBFREE    2
+#define CONFIG_SYS_NAND_BASE           0x520000000
+#define CONFIG_SYS_NAND_BASE_PHYS      0x20000000
+
+#define CONFIG_SYS_NAND_CSPR_EXT       (0x0)
+#define CONFIG_SYS_NAND_CSPR   (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+                               | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
+                               | CSPR_MSEL_NAND        /* MSEL = NAND */ \
+                               | CSPR_V)
+#define CONFIG_SYS_NAND_AMASK  IFC_AMASK(64 * 1024)
+
+#define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
+                               | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
+                               | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
+                               | CSOR_NAND_RAL_3       /* RAL = 2Byes */ \
+                               | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
+                               | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
+                               | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
+
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* ONFI NAND Flash mode0 Timing Params */
+#define CONFIG_SYS_NAND_FTIM0          (FTIM0_NAND_TCCST(0x07) | \
+                                       FTIM0_NAND_TWP(0x18)   | \
+                                       FTIM0_NAND_TWCHT(0x07) | \
+                                       FTIM0_NAND_TWH(0x0a))
+#define CONFIG_SYS_NAND_FTIM1          (FTIM1_NAND_TADLE(0x32) | \
+                                       FTIM1_NAND_TWBE(0x39)  | \
+                                       FTIM1_NAND_TRR(0x0e)   | \
+                                       FTIM1_NAND_TRP(0x18))
+#define CONFIG_SYS_NAND_FTIM2          (FTIM2_NAND_TRAD(0x0f) | \
+                                       FTIM2_NAND_TREH(0x0a) | \
+                                       FTIM2_NAND_TWHRE(0x1e))
+#define CONFIG_SYS_NAND_FTIM3          0x0
+
+#define CONFIG_SYS_NAND_BASE_LIST      { CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE     1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_CMD_NAND
+
+#define CONFIG_SYS_NAND_BLOCK_SIZE     (128 * 1024)
+
 #define CONFIG_SYS_CSPR0_EXT           CONFIG_SYS_NOR0_CSPR_EXT
 #define CONFIG_SYS_CSPR0               CONFIG_SYS_NOR0_CSPR_EARLY
 #define CONFIG_SYS_CSPR0_FINAL         CONFIG_SYS_NOR0_CSPR
@@ -167,6 +243,7 @@
 
 /* Miscellaneous configurable options */
 #define CONFIG_SYS_LOAD_ADDR   (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
+#define CONFIG_ARCH_EARLY_INIT_R
 
 /* Physical Memory Map */
 /* fixme: these need to be checked against the board */
@@ -174,9 +251,7 @@
 #define CONFIG_SYS_CLK_FREQ    133333333
 
 
-#define CONFIG_NR_DRAM_BANKS           2
-
-#define CONFIG_SYS_HZ                  1000
+#define CONFIG_NR_DRAM_BANKS           3
 
 #define CONFIG_HWCONFIG
 #define HWCONFIG_BUFFER_SIZE           128