ti_omap4_common.h: Switch to CONFIG_OMAP_SERIAL for non-SPL DM_SERIAL

[u-boot] / include / configs / ls2085aqds.h

diff --git a/include/configs/ls2085aqds.h b/include/configs/ls2085aqds.h
index f818570e5567f75c415608acab513958d85152a6..f7f38700323fd8f7341d47d7b0327dec531150b4 100644 (file)
--- a/include/configs/ls2085aqds.h
+++ b/include/configs/ls2085aqds.h
@@ -355,6 +355,23 @@ unsigned long get_board_ddr_clk(void);
 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
 
+#define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0
+#define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1
+#define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2
+#define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3
+#define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4
+#define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5
+#define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6
+#define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7
+#define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8
+#define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9
+#define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa
+#define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb
+#define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc
+#define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd
+#define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe
+#define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf
+
 #define CONFIG_MII             /* MII PHY management */
 #define CONFIG_ETHPRIME                "DPNI1"
 #define CONFIG_PHY_GIGE                /* Include GbE speed/duplex detection */