86xx: XPedite5170 board support

[u-boot] / include / configs / m501sk.h

diff --git a/include/configs/m501sk.h b/include/configs/m501sk.h
index f09214dce9c37d5b76c57f4a2653a5e541000755..1e7d90ed98dc5af260f9bf8a148b5d4c041ffdbe 100644 (file)
--- a/include/configs/m501sk.h
+++ b/include/configs/m501sk.h
@@ -41,6 +41,39 @@
 #define CONFIG_INITRD_TAG              1
 
 #define CONFIG_MENUPROMPT              "."
+/*
+ * LowLevel Init
+ */
+#define CONFIG_SYS_USE_MAIN_OSCILLATOR         1
+/* flash */
+#define CONFIG_SYS_MC_PUIA_VAL 0x00000000
+#define CONFIG_SYS_MC_PUP_VAL  0x00000000
+#define CONFIG_SYS_MC_PUER_VAL 0x00000000
+#define CONFIG_SYS_MC_ASR_VAL  0x00000000
+#define CONFIG_SYS_MC_AASR_VAL 0x00000000
+#define CONFIG_SYS_EBI_CFGR_VAL        0x00000000
+#define CONFIG_SYS_SMC_CSR0_VAL        0x00003284 /* 16bit, 2 TDF, 4 WS */
+
+/* clocks */
+#define CONFIG_SYS_PLLAR_VAL   0x20263E04 /* 179.712000 MHz for PCK */
+#define CONFIG_SYS_PLLBR_VAL   0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
+/* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */
+#define CONFIG_SYS_MCKR_VAL    0x00000202
+
+/* sdram */
+#define CONFIG_SYS_PIOC_ASR_VAL        0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
+#define CONFIG_SYS_PIOC_BSR_VAL        0x00000000
+#define CONFIG_SYS_PIOC_PDR_VAL        0xFFFF0000
+#define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS1=CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRC_CR_VAL 0x2188c155 /* set up the CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRAM       0x20000000 /* address of the CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRAM1      0x20000080 /* address of the CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRAM_VAL   0x00000000 /* value written to CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */
+#define CONFIG_SYS_SDRC_MR_VAL1        0x00000004 /* refresh */
+#define CONFIG_SYS_SDRC_MR_VAL2        0x00000003 /* Load Mode Register */
+#define CONFIG_SYS_SDRC_MR_VAL3        0x00000000 /* Normal Mode */
+#define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
 
 /*
  * Size of malloc() pool
@@ -77,6 +110,7 @@
 #define CONFIG_CMC_PU2
 
 /* define one of these to choose the DBGU, USART0  or USART1 as console */
+#define CONFIG_AT91RM9200_USART
 #define CONFIG_DBGU
 #undef CONFIG_USART0
 #undef CONFIG_USART1
@@ -121,7 +155,7 @@
 #define CONFIG_CMD_IMI
 #define CONFIG_CMD_NFS
 #define CONFIG_CMD_FLASH
-#define CONFIG_CMD_ENV
+#define CONFIG_CMD_SAVEENV
 
 #define CONFIG_SYS_HUSH_PARSER
 #define CONFIG_AUTO_COMPLETE