nios2: Split timer code into timer.c

[u-boot] / include / configs / maxbcm.h

diff --git a/include/configs/maxbcm.h b/include/configs/maxbcm.h
index 0839d39a396c91c1b1f87404aceba6af7810f8f9..3bed9c7ca403d7fce054201c9a3ada3a4acf8aa5 100644 (file)
--- a/include/configs/maxbcm.h
+++ b/include/configs/maxbcm.h
@@ -11,11 +11,18 @@
  * High Level Configuration Options (easy to change)
  */
 #define CONFIG_ARMADA_XP               /* SOC Family Name */
+#ifdef CONFIG_SPL_BUILD
 #define CONFIG_SKIP_LOWLEVEL_INIT      /* disable board lowlevel_init */
+#endif
 #define CONFIG_SYS_GENERIC_BOARD
 #define CONFIG_DISPLAY_BOARDINFO_LATE
 
-#define        CONFIG_SYS_TEXT_BASE    0x04000000
+/*
+ * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
+ * for DDR ECC byte filling in the SPL before loading the main
+ * U-Boot into it.
+ */
+#define        CONFIG_SYS_TEXT_BASE    0x00800000
 #define CONFIG_SYS_TCLK                250000000       /* 250MHz */
 
 /*
@@ -43,7 +50,6 @@
 #define CONFIG_SF_DEFAULT_MODE         SPI_MODE_3
 #define CONFIG_SPI_FLASH_STMICRO
 #define CONFIG_SPI_FLASH_SPANSION
-#define CONFIG_SPI_FLASH_BAR
 
 /* Environment in SPI NOR flash */
 #define CONFIG_ENV_IS_IN_SPI_FLASH
@@ -109,7 +115,7 @@
 #define CONFIG_SYS_SPI_U_BOOT_OFFS     0x20000
 
 /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
-#define CONFIG_SYS_MVEBU_DDR
+#define CONFIG_SYS_MVEBU_DDR_AXP
 #define CONFIG_DDR_FIXED_SIZE          (1 << 20)       /* 1GiB */
 
 #endif /* _CONFIG_DB_MV7846MP_GP_H */