FSL DDR: Convert STXSSA to new DDR code.

[u-boot] / include / configs / ml300.h

diff --git a/include/configs/ml300.h b/include/configs/ml300.h
index 0183041842af27139d5f25a5d2a052a7ee1d25c2..319923ad6efe9d6444440932c840303de8b1dd05 100644 (file)
--- a/include/configs/ml300.h
+++ b/include/configs/ml300.h
@@ -54,6 +54,7 @@
 
 #define CONFIG_405             1       /* This is a PPC405 CPU         */
 #define CONFIG_4xx             1       /* ...member of PPC4xx family   */
+#define CONFIG_XILINX_405      1
 #define CONFIG_XILINX_ML300    1       /* ...on a Xilinx ML300 board   */
 
 #define CONFIG_SYSTEMACE       1
@@ -159,12 +160,6 @@
  */
 #define CFG_BOOTMAPSZ          (8 << 20)       /* Initial Memory map for Linux */
 
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE                16384   /* For AMCC 405 CPUs    */
-#define CFG_CACHELINE_SIZE     32      /* ...                  */
-
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */