MX: RTC13783 uses general function to access PMIC

[u-boot] / include / configs / mx31pdk.h

diff --git a/include/configs/mx31pdk.h b/include/configs/mx31pdk.h
index 7167e9d0db213c3de3dd8989b0b6f4d0043704b8..0414cc37a7a94388950b576b9d4ddd47bd20c655 100644 (file)
--- a/include/configs/mx31pdk.h
+++ b/include/configs/mx31pdk.h
@@ -30,6 +30,8 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+#include <asm/arch/mx31-regs.h>
+
 /* High Level Configuration Options */
 #define CONFIG_ARM1136         1       /* This is an arm1136 CPU core */
 #define CONFIG_MX31            1       /* in a mx31 */
@@ -43,15 +45,15 @@
 #define CONFIG_SETUP_MEMORY_TAGS       1
 #define CONFIG_INITRD_TAG              1
 
-/* No support for NAND boot for i.MX31 PDK yet, so we rely on some other
- * program to initialize the SDRAM.
- */
+#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
 #define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SKIP_RELOCATE_UBOOT
+#endif
 
 /*
  * Size of malloc() pool
  */
-#define CONFIG_SYS_MALLOC_LEN          (CONFIG_ENV_SIZE + 128 * 1024)
+#define CONFIG_SYS_MALLOC_LEN          (2*CONFIG_ENV_SIZE + 2 * 128 * 1024)
 /* Bytes reserved for initial data */
 #define CONFIG_SYS_GBL_DATA_SIZE       128
 
@@ -67,12 +69,13 @@
 #define CONFIG_DEFAULT_SPI_BUS 1
 #define CONFIG_DEFAULT_SPI_MODE        (SPI_MODE_2 | SPI_CS_HIGH)
 
+#define CONFIG_FSL_PMIC
+#define CONFIG_FSL_PMIC_BUS    1
+#define CONFIG_FSL_PMIC_CS     2
+#define CONFIG_FSL_PMIC_CLK    1000000
+#define CONFIG_FSL_PMIC_MODE   (SPI_MODE_2 | SPI_CS_HIGH)
 #define CONFIG_RTC_MC13783     1
 
-/* MC13783 connected to CSPI2 and SS2 */
-#define CONFIG_MC13783_SPI_BUS 1
-#define CONFIG_MC13783_SPI_CS  2
-
 /* allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_CONS_INDEX              1
@@ -89,6 +92,7 @@
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_SPI
 #define CONFIG_CMD_DATE
+#define CONFIG_CMD_NAND
 
 /*
  * Disabled due to compilation errors in cmd_bootm.c (IMLS seems to require
@@ -104,11 +108,15 @@
                "ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0"     \
        "bootcmd=run bootcmd_net\0"                                     \
        "bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; "     \
-               "tftpboot 0x81000000 uImage-mx31; bootm\0"
+               "tftpboot 0x81000000 uImage-mx31; bootm\0"              \
+       "prg_uboot=tftpboot 0x81000000 u-boot-nand.bin; "               \
+               "nand erase 0x0 0x40000; "                              \
+               "nand write 0x81000000 0x0 0x40000\0"
 
-#define CONFIG_DRIVER_SMC911X          1
-#define CONFIG_DRIVER_SMC911X_BASE     0xB6000000
-#define CONFIG_DRIVER_SMC911X_32_BIT   1
+#define CONFIG_NET_MULTI
+#define CONFIG_SMC911X         1
+#define CONFIG_SMC911X_BASE    0xB6000000
+#define CONFIG_SMC911X_32_BIT  1
 
 /*
  * Miscellaneous configurable options
@@ -155,8 +163,56 @@
 /* No NOR flash present */
 #define CONFIG_SYS_NO_FLASH    1
 
-#define CONFIG_ENV_IS_NOWHERE  1
+#define CONFIG_ENV_IS_IN_NAND          1
+#define CONFIG_ENV_OFFSET              0x40000
+#define CONFIG_ENV_OFFSET_REDUND       0x60000
+#define CONFIG_ENV_SIZE                        (128 * 1024)
 
-#define CONFIG_ENV_SIZE                (128 * 1024)
+/*
+ * NAND driver
+ */
+#define CONFIG_NAND_MXC
+#define CONFIG_MXC_NAND_REGS_BASE      NFC_BASE_ADDR
+#define CONFIG_SYS_MAX_NAND_DEVICE     1
+#define CONFIG_SYS_NAND_BASE           NFC_BASE_ADDR
+#define CONFIG_MXC_NAND_HWECC
+#define CONFIG_SYS_NAND_LARGEPAGE
+
+/* NAND configuration for the NAND_SPL */
+
+/* Start copying real U-boot from the second page */
+#define CONFIG_SYS_NAND_U_BOOT_OFFS    0x800
+#define CONFIG_SYS_NAND_U_BOOT_SIZE    0x30000
+/* Load U-Boot to this address */
+#define CONFIG_SYS_NAND_U_BOOT_DST     0x87f00000
+#define CONFIG_SYS_NAND_U_BOOT_START   CONFIG_SYS_NAND_U_BOOT_DST
+
+#define CONFIG_SYS_NAND_PAGE_SIZE      0x800
+#define CONFIG_SYS_NAND_BLOCK_SIZE     (128 * 1024)
+#define CONFIG_SYS_NAND_PAGE_COUNT     64
+#define CONFIG_SYS_NAND_SIZE           (256 * 1024 * 1024)
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS  0
+
+
+/* Configuration of lowlevel_init.S (clocks and SDRAM) */
+#define CCM_CCMR_SETUP         0x074B0BF5
+#define CCM_PDR0_SETUP_532MHZ  (PDR0_CSI_PODF(0x1ff) | PDR0_PER_PODF(7) | \
+                                PDR0_HSP_PODF(3) | PDR0_NFC_PODF(5) |     \
+                                PDR0_IPG_PODF(1) | PDR0_MAX_PODF(3) |     \
+                                PDR0_MCU_PODF(0))
+#define CCM_MPCTL_SETUP_532MHZ (PLL_PD(0) | PLL_MFD(51) | PLL_MFI(10) |   \
+                                PLL_MFN(12))
+
+#define ESDMISC_MDDR_SETUP     0x00000004
+#define ESDMISC_MDDR_RESET_DL  0x0000000c
+#define ESDCFG0_MDDR_SETUP     0x006ac73a
+
+#define ESDCTL_ROW_COL         (ESDCTL_SDE | ESDCTL_ROW(2) | ESDCTL_COL(2))
+#define ESDCTL_SETTINGS                (ESDCTL_ROW_COL | ESDCTL_SREFR(3) | \
+                                ESDCTL_DSIZ(2) | ESDCTL_BL(1))
+#define ESDCTL_PRECHARGE       (ESDCTL_ROW_COL | ESDCTL_CMD_PRECHARGE)
+#define ESDCTL_AUTOREFRESH     (ESDCTL_ROW_COL | ESDCTL_CMD_AUTOREFRESH)
+#define ESDCTL_LOADMODEREG     (ESDCTL_ROW_COL | ESDCTL_CMD_LOADMODEREG)
+#define ESDCTL_RW              ESDCTL_SETTINGS
 
 #endif /* __CONFIG_H */