]> git.sur5r.net Git - u-boot/blobdiff - include/configs/mx7dsabresd.h
board: Add Microchip PIC32MZ[DA]-Starter-Kit board.
[u-boot] / include / configs / mx7dsabresd.h
index 96cd9e9960add2e3f1142dcc22699997009a9cf8..d23e4f3c407bdb576aa9ecc53fd31c1fd3943543 100644 (file)
@@ -87,6 +87,7 @@
        "fdt_addr=0x83000000\0" \
        "boot_fdt=try\0" \
        "ip_dyn=yes\0" \
+       "videomode=video=ctfb:x:480,y:272,depth:24,pclk:108695,le:8,ri:4,up:2,lo:4,hs:41,vs:10,sync:0,vmode:0\0" \
        "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
        "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
        "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
 #define CONFIG_SYS_NO_FLASH
 #define CONFIG_ENV_SIZE                        SZ_8K
 #define CONFIG_ENV_IS_IN_MMC
+
+/*
+ * If want to use nand, define CONFIG_NAND_MXS and rework board
+ * to support nand, since emmc has pin conflicts with nand
+ */
+#ifdef CONFIG_NAND_MXS
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_NAND_TRIMFFS
+
+/* NAND stuff */
+#define CONFIG_SYS_MAX_NAND_DEVICE     1
+#define CONFIG_SYS_NAND_BASE           0x40000000
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* DMA stuff, needed for GPMI/MXS NAND support */
+#define CONFIG_APBH_DMA
+#define CONFIG_APBH_DMA_BURST
+#define CONFIG_APBH_DMA_BURST8
+#endif
+
 #define CONFIG_ENV_OFFSET              (8 * SZ_64K)
+#ifdef CONFIG_NAND_MXS
+#define CONFIG_SYS_FSL_USDHC_NUM       1
+#else
 #define CONFIG_SYS_FSL_USDHC_NUM       2
+#endif
 
 #define CONFIG_SYS_MMC_ENV_DEV         0   /* USDHC1 */
 #define CONFIG_SYS_MMC_ENV_PART                0       /* user area */
 #define CONFIG_DFU_MMC
 #define CONFIG_DFU_RAM
 
+#define CONFIG_VIDEO
+#ifdef CONFIG_VIDEO
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VIDEO_MXS
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_SW_CURSOR
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASH_SCREEN_ALIGN
+#define CONFIG_CMD_BMP
+#define CONFIG_BMP_16BPP
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_VIDEO_BMP_LOGO
+#endif
+
+#ifdef CONFIG_FSL_QSPI
+#define CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_MACRONIX
+#define CONFIG_SPI_FLASH_BAR
+#define CONFIG_SF_DEFAULT_BUS          0
+#define CONFIG_SF_DEFAULT_CS           0
+#define CONFIG_SF_DEFAULT_SPEED                40000000
+#define CONFIG_SF_DEFAULT_MODE         SPI_MODE_0
+#define FSL_QSPI_FLASH_NUM             1
+#define FSL_QSPI_FLASH_SIZE            SZ_64M
+#define QSPI0_BASE_ADDR                        QSPI1_IPS_BASE_ADDR
+#define QSPI0_AMBA_BASE                        QSPI0_ARB_BASE_ADDR
+#endif
+
 #endif /* __CONFIG_H */