sunxi: Fix reset hang on sun5i

[u-boot] / include / configs / mxs.h

diff --git a/include/configs/mxs.h b/include/configs/mxs.h
index a684166502fc5d6de05a5cd8a6f602bce9085261..8bce28fe2048f9abeb1b0de154871ee790404f87 100644 (file)
--- a/include/configs/mxs.h
+++ b/include/configs/mxs.h
@@ -40,9 +40,7 @@
 /*
  * CPU specifics
  */
-
-/* Ticks per second */
-#define CONFIG_SYS_HZ          1000
+#define CONFIG_SYS_GENERIC_BOARD
 
 /* MXS uses FDT */
 #define CONFIG_OF_LIBFDT
@@ -62,7 +60,6 @@
 
 /* Memory sizes */
 #define CONFIG_SYS_MALLOC_LEN          0x00400000      /* 4 MB for malloc */
-#define CONFIG_SYS_GBL_DATA_SIZE       128             /* Initial data */
 #define CONFIG_SYS_MEMTEST_START       0x40000000      /* Memtest start adr */
 #define CONFIG_SYS_MEMTEST_END         0x40400000      /* 4 MB RAM test */
 
@@ -84,13 +81,20 @@
  * We need to sacrifice first 4 bytes of RAM here to avoid triggering some
  * strange BUG in ROM corrupting first 4 bytes of RAM when loading U-Boot
  * binary. In case there was more of this mess, 0x100 bytes are skipped.
+ *
+ * In case of a HAB boot, we cannot for some weird reason use the first 4KiB
+ * of DRAM when loading. Moreover, we use the first 4 KiB for IVT and CST
+ * blocks, thus U-Boot starts at offset +8 KiB of DRAM start.
+ *
+ * As for the SPL, we must avoid the first 4 KiB as well, but we load the
+ * IVT and CST to 0x8000, so we don't need to waste the subsequent 4 KiB.
  */
-#define CONFIG_SYS_TEXT_BASE           0x40000100
+#define CONFIG_SYS_TEXT_BASE           0x40002000
+#define CONFIG_SPL_TEXT_BASE           0x00001000
 
 /* U-Boot general configuration */
 #define CONFIG_SYS_LONGHELP
 #ifndef CONFIG_SYS_PROMPT
-#define CONFIG_SYS_PROMPT      "=> "
 #endif
 #define CONFIG_SYS_CBSIZE      1024            /* Console I/O buffer size */
 #define CONFIG_SYS_PBSIZE      \
@@ -119,11 +123,16 @@
 /* GPIO */
 #define CONFIG_MXS_GPIO
 
-/* DUART Serial Driver */
+/*
+ * DUART Serial Driver.
+ * Conflicts with AUART driver which can be set by board.
+ */
+#ifndef CONFIG_MXS_AUART
 #define CONFIG_PL011_SERIAL
 #define CONFIG_PL011_CLOCK             24000000
 #define CONFIG_PL01x_PORTS             { (void *)MXS_UARTDBG_BASE }
 #define CONFIG_CONS_INDEX              0
+#endif
 /* Default baudrate can be overriden by board! */
 #ifndef CONFIG_BAUDRATE
 #define CONFIG_BAUDRATE                        115200
@@ -174,6 +183,11 @@
 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
 #endif
 
+/* OCOTP */
+#ifdef CONFIG_CMD_FUSE
+#define CONFIG_MXS_OCOTP
+#endif
+
 /* SPI */
 #ifdef CONFIG_CMD_SPI
 #define CONFIG_HARD_SPI