*/
#define CONFIG_OMAP 1 /* in a TI OMAP core */
#define CONFIG_OMAP34XX 1 /* which is a 34XX */
-#define CONFIG_OMAP3430 1 /* which is in a 3430 */
#define CONFIG_OMAP3_OVERO 1 /* working with overo */
#define CONFIG_SDRC /* The chip has SDRC controller */
#define CONFIG_OMAP_HSMMC 1
#define CONFIG_DOS_PARTITION 1
-/* DDR - I use Micron DDR */
-#define CONFIG_OMAP3_MICRON_DDR 1
-
/* commands to include */
#include <config_cmd_default.h>
"mmcdev=0\0" \
"mmcroot=/dev/mmcblk0p2 rw\0" \
"mmcrootfstype=ext3 rootwait\0" \
- "nandroot=/dev/mtdblock4 rw\0" \
- "nandrootfstype=jffs2\0" \
+ "nandroot=ubi0:rootfs ubi.mtd=4\0" \
+ "nandrootfstype=ubifs\0" \
"mmcargs=setenv bootargs console=${console} " \
"${optargs} " \
"mpurate=${mpurate} " \
* The stack sizes are set up in start.S using the settings below
*/
#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack 4 KiB */
-#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack 4 KiB */
-#endif
/*-----------------------------------------------------------------------
* Physical Memory Map
#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */
#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
-/* SDRAM Bank Allocation method */
-#define SDRC_R_B_C 1
-
/*-----------------------------------------------------------------------
* FLASH and environment organization
*/
CONFIG_SYS_INIT_RAM_SIZE - \
GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_CACHELINE_SIZE 64
+
#endif /* __CONFIG_H */