TI:armv7: Enable CONFIG_CMD_GPIO

[u-boot] / include / configs / omap3_zoom2.h

diff --git a/include/configs/omap3_zoom2.h b/include/configs/omap3_zoom2.h
index d6814248ed18e831d8e998910f9b0b21b439e2fe..cb8c7ec6f0667a3e7e307901826199538fa4d314 100644 (file)
--- a/include/configs/omap3_zoom2.h
+++ b/include/configs/omap3_zoom2.h
@@ -8,23 +8,7 @@
  *
  * Configuration settings for the TI OMAP3430 Zoom II board.
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #ifndef __CONFIG_H
@@ -37,6 +21,7 @@
 #define CONFIG_OMAP34XX                1       /* which is a 34XX */
 #define CONFIG_OMAP3_ZOOM2     1       /* working with Zoom II */
 #define CONFIG_OMAP_GPIO
+#define CONFIG_OMAP_COMMON
 
 #define CONFIG_SDRC    /* The chip has SDRC controller */
 
@@ -156,8 +141,6 @@
 #define CONFIG_HARD_I2C                        1
 #define CONFIG_SYS_I2C_SPEED           100000
 #define CONFIG_SYS_I2C_SLAVE           1
-#define CONFIG_SYS_I2C_BUS             0
-#define CONFIG_SYS_I2C_BUS_SELECT      1
 #define CONFIG_DRIVER_OMAP34XX_I2C     1
 
 /*
@@ -221,7 +204,6 @@
  */
 #define CONFIG_NR_DRAM_BANKS   2       /* CS1 may or may not be populated */
 #define PHYS_SDRAM_1           OMAP34XX_SDRC_CS0
-#define PHYS_SDRAM_1_SIZE      (32 << 20)      /* at least 32 MiB */
 #define PHYS_SDRAM_2           OMAP34XX_SDRC_CS1
 
 /*-----------------------------------------------------------------------