Merge branch 'master' of git://git.denx.de/u-boot-arm

[u-boot] / include / configs / omap730.h

diff --git a/include/configs/omap730.h b/include/configs/omap730.h
index 5fbbeb025e21914d8b3cbc691d55ebf07026fcb1..b54e0fb2dae4385049a601b28a587a23b3a41b86 100644 (file)
--- a/include/configs/omap730.h
+++ b/include/configs/omap730.h
@@ -7,35 +7,13 @@
  * Author: MPC-Data Limited
  *        Dave Peverley
  *
- *  This program is free software; you can redistribute         it and/or modify it
- *  under  the terms of         the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the License, or (at your
- *  option) any later version.
- *
- *  THIS  SOFTWARE  IS PROVIDED          ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
- *  WARRANTIES,          INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
- *  NO EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
- *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- *  NOT LIMITED          TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
- *  USE, DATA, OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- *  ANY THEORY OF LIABILITY, WHETHER IN         CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *  You should have received a copy of the  GNU General Public License along
- *  with this program; if not, write  to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
-
 #ifndef __INCLUDED_OMAP730_H
 #define __INCLUDED_OMAP730_H
 
-#include <asm/arch/sizes.h>
-
-
-
+#include <asm/sizes.h>
 
 /***************************************************************************
  * OMAP730 Configuration Registers
@@ -87,9 +65,6 @@
 #define DEBUG2                            ((unsigned int)(0xFFFE10E4))
 #define DEBUG_DMA_IRQ                     ((unsigned int)(0xFFFE10E8))
 
-
-
-
 /***************************************************************************
  * OMAP730 EMIFS Registers                                       (TRM 2.5.7)
  **************************************************************************/
@@ -114,8 +89,6 @@
 #define FLASH_ACFG_2_1             (TCMIF_BASE + 0x58)
 #define FLASH_ACFG_3_1             (TCMIF_BASE + 0x5C)
 
-
-
 /***************************************************************************
  * OMAP730 Interrupt handlers
  **************************************************************************/
@@ -123,12 +96,10 @@
 #define OMAP_IH1_BASE          0xFFFECB00     /* MPU Level 1 IRQ handler */
 #define OMAP_IH2_BASE           0xfffe0000
 
-
-
 /***************************************************************************
  * OMAP730 Timers
  *
- * There are three general purpose OS timers in the 730 that can be 
+ * There are three general purpose OS timers in the 730 that can be
  * configured in autoreload or one-shot modes.
  **************************************************************************/
 
@@ -161,13 +132,11 @@
 /* MPU_CNTL_TIMER register bits */
 #define MPUTIM_FREE               (1<<6)
 #define MPUTIM_CLOCK_ENABLE       (1<<5)
-#define MPUTIM_PTV_MASK           (0x7<<PTV_BIT)
+#define MPUTIM_PTV_MASK           (0x7<<MPUTIM_PTV_BIT)
 #define MPUTIM_PTV_BIT            2
 #define MPUTIM_AR                 (1<<1)
 #define MPUTIM_ST                 (1<<0)
 
-
-
 /***************************************************************************
  * OMAP730 GPIO
  *
@@ -231,9 +200,6 @@
 #define GPIO_INTERRUPT_MASK_6        ((unsigned int)(OMAP730_GPIO_BASE_6 + GPIO_INTERRUPT_MASK))
 #define GPIO_INTERRUPT_STATUS_6      ((unsigned int)(OMAP730_GPIO_BASE_6 + GPIO_INTERRUPT_STATUS))
 
-
-
-
 /***************************************************************************
  * OMAP730 Watchdog timers
  **************************************************************************/
@@ -244,16 +210,13 @@
 #define WDTIM_READ                 (WDTIM_BASE + 0x04)    /* MPU_READ_TIMER */
 #define WDTIM_MODE                 (WDTIM_BASE + 0x08)    /* MPU_TIMER_MODE */
 
-
-
-
 /***************************************************************************
  * OMAP730 Interrupt Registers
  **************************************************************************/
 
 /* Interrupt Register offsets */
 
-#define IRQ_ITR                               0x00  
+#define IRQ_ITR                               0x00
 #define IRQ_MIR                               0x04
 #define IRQ_SIR_IRQ                           0x10
 #define IRQ_SIR_FIQ                           0x14
@@ -265,14 +228,12 @@
 #define REG_IHL1_MIR  (OMAP_IH1_BASE + IRQ_MIR)
 #define REG_IHL2_MIR  (OMAP_IH2_BASE + IRQ_MIR)
 
-
 /***************************************************************************
  * OMAP730 Intersystem Communication Register                      (TRM 4.5)
  **************************************************************************/
- 
- 
+
 #define ICR_BASE                   0xFFFBB800
- 
+
 #define M_ICR                      (ICR_BASE + 0x00)
 #define G_ICR                      (ICR_BASE + 0x02)
 #define M_CTL                      (ICR_BASE + 0x04)
@@ -282,6 +243,4 @@
 #define RM_BA                      (ICR_BASE + 0x0E)
 #define SSPI_TAS                   (ICR_BASE + 0x12)
 
-
-
 #endif /* ! __INCLUDED_OMAP730_H */