]> git.sur5r.net Git - u-boot/blobdiff - include/configs/omapl138_lcdk.h
Convert CONFIG_DAVINCI_SPI to Kconfig
[u-boot] / include / configs / omapl138_lcdk.h
index 08e7deb30f16cf0aeb747f93642ef3b4d5ca9361..505b164f9b5854635d1da203c29ada42f85be8f0 100644 (file)
 #define CONFIG_SYS_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
 
 #define CONFIG_SPI
-#define CONFIG_DAVINCI_SPI
 #define CONFIG_SYS_SPI_BASE            DAVINCI_SPI1_BASE
 #define CONFIG_SYS_SPI_CLK             clk_get(DAVINCI_SPI1_CLKID)
 #define CONFIG_SF_DEFAULT_SPEED                30000000
 #define        CONFIG_SYS_NAND_USE_FLASH_BBT
 #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
 #define        CONFIG_SYS_NAND_PAGE_2K
-#define        CONFIG_SYS_NAND_BUSWIDTH_16BIT
 #define CONFIG_SYS_NAND_CS             3
 #define CONFIG_SYS_NAND_BASE           DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
 #define CONFIG_SYS_NAND_MASK_CLE       0x10
 #define CONFIG_SPL_NAND_BASE
 #define CONFIG_SPL_NAND_DRIVERS
 #define CONFIG_SPL_NAND_ECC
-#define CONFIG_SPL_NAND_SIMPLE
 #define CONFIG_SPL_NAND_LOAD
 #endif
 
 #define CONFIG_MISC_INIT_R
 #define CONFIG_BOOTFILE                "zImage" /* Boot file name */
 #define CONFIG_SYS_CBSIZE      1024 /* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE      (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
-#define CONFIG_SYS_MAXARGS     16 /* max number of command args */
 #define CONFIG_SYS_BARGSIZE    CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
 #define CONFIG_SYS_LOAD_ADDR   (PHYS_SDRAM_1 + 0x700000)
 #define CONFIG_AUTO_COMPLETE
        "boot_fit=0\0" \
        "console=ttyS2,115200n8\0"
 
-/*
- * U-Boot commands
- */
-#define CONFIG_CMD_SAVES
 #ifdef CONFIG_CMD_BDI
 #define CONFIG_CLOCKS
 #endif
 #define CONFIG_SYS_SPL_MALLOC_START    (CONFIG_SYS_TEXT_BASE - \
                                                CONFIG_SYS_MALLOC_LEN)
 #define CONFIG_SYS_SPL_MALLOC_SIZE     CONFIG_SYS_MALLOC_LEN
-#define CONFIG_SPL_LDSCRIPT    "board/$(BOARDDIR)/u-boot-spl-da850evm.lds"
 #define CONFIG_SPL_STACK       0x8001ff00
 #define CONFIG_SPL_TEXT_BASE   0x80000000
 #define CONFIG_SPL_MAX_FOOTPRINT       32768